Michael O Creighton

US Patent:

7126155, Oct 24, 2006

Filed:

Oct 27, 2004

Appl. No.:

10/975133

Inventors:

Bashu Kanal - Southboro MA, US
Michael Creighton - Charlton MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

H01L 23/58

US Classification:

257 48, 257797, 257E21521, 324158

Abstract:

A test point on a printed circuit board includes at least one connection to the power plane having first and second interconnected pads disposed on opposing sides of the power plane, and at least one connection to the ground plane having third and fourth interconnected pads disposed on opposing sides of the ground plane. The first and second interconnected pads provide parallel paths to the power plane, thereby reducing the impedance presented to test equipment. Similarly, The third and fourth interconnected pads provide parallel paths to the ground plane. The test point may be implemented with multiple ground plane connections disposed symmetrically around a power plane connection. For example, first and second ground plane connections may be disposed on opposing sides of a power plane connection to provide shielding to the power plane connection, thereby reducing the inductive loop associated with probe parasitics.