Michael Richard Davies

US Patent:

20180174026, Jun 21, 2018

Filed:

Dec 20, 2016

Appl. No.:

15/385026

Inventors:

Michael I. Davies - Portland OR, US

International Classification:

G06N 3/063

Abstract:

An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.

US Patent:

20180174027, Jun 21, 2018

Filed:

Dec 20, 2016

Appl. No.:

15/385038

Inventors:

Michael I. Davies - Portland OR, US

International Classification:

G06N 3/063
G06N 3/04
G06N 3/08

Abstract:

An electronic neural core circuit is provided, comprising a processor, and a memory. The memory comprises a plurality of neural compartments, each compartment comprising a first state variable representing a first state of the neural compartment, and a second state variable representing a second state of the neural compartment. The processor is configured to, for a first neural compartment: receive a synaptic input, perform first and second state variable operations, join operations utilizing input from state variables from another compartment that has been previously processed, thereby producing a join operation results, and produce a state variable output.

US Patent:

20180174028, Jun 21, 2018

Filed:

Dec 20, 2016

Appl. No.:

15/385541

Inventors:

- Santa Clara CA, US
Michael Davies - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06N 3/063
G06N 3/04

Abstract:

A spiking neural network (SNN) includes artificial neurons interconnected by artificial synapses, where the spiking neural network is defined to correspond to one or more numerical matrices, and neurons of the SNN include attributes to inhibit accumulation of potential at the respective neuron responsive to spike messages. Synapses of the SNN have weight values corresponding to one or more numerical matrices. Inputs are provided to the SNN corresponding to a numerical vector. Steady state spiking rates are determined for at least a subset of the neurons and a sparse basis vector is determined based on the steady state spiking rate values.

US Patent:

20180174033, Jun 21, 2018

Filed:

Dec 20, 2016

Appl. No.:

15/385057

Inventors:

Michael I. Davies - Portland OR, US

International Classification:

G06N 3/063
G06N 3/04
G06N 3/08

Abstract:

An electronic neuromorphic core processor circuit and related method include a dendrite circuit comprising an input that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit associates the identifier with a set of synaptic connections, possibly shared hierarchically over populations of neurons defined implicitly by the mapping structures, that are read from the memory. The synaptic connections determine n-tuple information comprising a dendriteID, a weight, and a network delay time. A dendrite accumulator circuit accumulates weight values scheduled at the appropriate future time as identified by the n-tuple information and maps them to a soma compartment. A soma circuit maintains soma compartment state in response to the accumulated weight values scheduled for servicing and, when sufficiently activated, produces output spikes.

US Patent:

20180174039, Jun 21, 2018

Filed:

Dec 20, 2016

Appl. No.:

15/385170

Inventors:

Michael I Davies - Portland OR, US

International Classification:

G06N 3/08
G06N 3/063
G06N 3/04

Abstract:

Aspects of the embodiments are directed to computationally modeling a filtered temporal spike train trace in the digital domain. A current value of the trace, and a parameter defining temporal behavior of the trace, are each stored. A decay function of the trace is computed based on the parameter and on passage of discrete time increments. Stimulus signaling is received, and an input response function of the trace is computed based on the stimulus signaling. A stochastic computation of the trace decay function may be performed based on a generated randomization value. In some embodiments, a delayed computation of the trace decay function may be performed.

US Patent:

20180174040, Jun 21, 2018

Filed:

Dec 20, 2016

Appl. No.:

15/385219

Inventors:

Michael I. Davies - Portland OR, US
Andrew M. Lines - Portland OR, US

International Classification:

G06N 3/08
G06N 3/063

Abstract:

A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.