Michael L Day

Address:

3836 Mockingbird Ln, Dallas, TX 75205

VIN:

JN1CV6AP8AM400320

Make:

INFINITI

Model:

G37 SEDAN

Year:

2010

US Patent:

6452789, Sep 17, 2002

Filed:

Apr 29, 2000

Appl. No.:

09/562593

Inventors:

Lisa Heid Pallotti - Plano TX
Eric C. Peterson - McKinney TX
Christian L Belady - McKinney TX
Terrel L. Morris - Garland TX
Michael C. Day - Allen TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

361683, 361727, 361788, 395401, 174158 R

Abstract:

The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.

US Patent:

6596948, Jul 22, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/560794

Inventors:

Stuart C. Haden - Lucas TX
Shaun L. Harris - McKinney TX
Michael C. Day - Allen TX
Lisa Heid Pallotti - Plano TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01R 1204

US Classification:

174262, 174260, 174255

Abstract:

A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.

US Patent:

6818835, Nov 16, 2004

Filed:

Apr 22, 2003

Appl. No.:

10/420572

Inventors:

Stuart C. Haden - Lucas TX
Shaun L. Harris - McKinney TX
Michael C. Day - Allen TX
Christian L Belady - McKinney TX
Lisa Heid Pallotti - Plano TX
Paul T. Artman - Dallas TX
Eric C. Peterson - McKinney TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H05K 103

US Classification:

174255, 174261

Abstract:

A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

US Patent:

7212424, May 1, 2007

Filed:

Mar 21, 2005

Appl. No.:

11/085693

Inventors:

Brian M. Johnson - Allen TX, US
John Nerl - Londonderry NH, US
Michael C. Day - Allen TX, US
Vicki L. Smith - NW Province, CM
Richard A. Schumacher - Dallas TX, US
Rajakrishnan Radjassamy - Plano TX, US
June E. Goodwin - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 5/06

US Classification:

365 63, 36523008, 361764, 716 15

Abstract:

One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

US Patent:

7475175, Jan 6, 2009

Filed:

Mar 15, 2004

Appl. No.:

10/800837

Inventors:

David A. Klein - Carrollton TX, US
Christian L. Belady - McKinney TX, US
Shaun L. Harris - McKinney TX, US
Michael C. Day - Allen TX, US
Jeffrey P. Christenson - Plano TX, US
Brent A. Boudreaux - Highland Village TX, US
Stuart C. Haden - Allen TX, US
Eric Peterson - McKinney TX, US
Jeffrey N. Metcalf - Frisco TX, US
James S. Wells - Windsor CO, US
Gary W. Williams - Rowlett TX, US
Paul A. Wirtzberger - Greenville TX, US
Roy M. Zeighami - McKinney TX, US
Greg Huff - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01L 23/34
H01L 23/12
H05K 7/20
G06F 13/00

US Classification:

710100, 257706, 257711, 361702, 361707, 361719

Abstract:

An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

US Patent:

7545651, Jun 9, 2009

Filed:

Apr 18, 2005

Appl. No.:

11/108245

Inventors:

June E. Goodwin - Plano TX, US
Michael C. Day - Allen TX, US
Brian M. Johnson - Allen TX, US
John A. Nerl - Londonderry NH, US
Richard A. Schumacher - Dallas TX, US
Vicki L. Smith - N.W. Province, CM

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H05K 1/18

US Classification:

361764, 361763, 361782, 361803, 365 51

Abstract:

A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

US Patent:

8118692, Feb 21, 2012

Filed:

Mar 12, 2010

Appl. No.:

12/661258

Inventors:

Michael L. Day - Garland TX, US
Dylan L. Day - Garland TX, US

International Classification:

A63B 69/00

US Classification:

473453, 473422, 473451

Abstract:

It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1. 27(b).

US Patent:

57615110, Jun 2, 1998

Filed:

Jan 28, 1994

Appl. No.:

8/187972

Inventors:

Jonathan J. Gibbons - Mountain View CA
Michael J. Day - Mountain View CA
Theodore C. Goldstein - Palo Alto CA
Michael J. Jordan - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 945

US Classification:

395705

Abstract:

The present invention provides a system and process for making use of pre-existing data-structures which represent a computer program, in a way which has the advantages of shortening the time and cost required to create a new version of the computer program. The pre-existing data-structure is modified to produce a shadow data-structure which contains only shadows of those elements or nodes of the pre-existing data-structure required to perform the tasks of the new version of the computer program. The present invention includes processes to make the data-structure of the original program shadowable; processes to use data from the original program compilation process in compiling the new version of the program, including processes to create a shadow data-structure; and processes to use the new version of the computer program along with the shadow data-structure to create the desired execution. This new version of the computer program is typically a tool for checking or observing the original program's execution in some manner. Moreover, the system and processes disclosed provide mechanisms for a software manufacturer to create type-safe versions of a connected collection of objects which are dynamically extensible.