Michael K Day

US Patent:

6820143, Nov 16, 2004

Filed:

Dec 17, 2002

Appl. No.:

10/322127

Inventors:

Michael Norman Day - Round Rock TX
Charles Ray Johns - Austin TX
James Allan Kahle - Austin TX
Peichun Peter Liu - Austin TX
David Shippy - Austin TX
Thuong Quang Truong - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 27, 712 32, 712 33

Abstract:

A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

US Patent:

6961820, Nov 1, 2005

Filed:

Feb 12, 2003

Appl. No.:

10/366440

Inventors:

Michael Norman Day - Round Rock TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
Peichun Peter Liu - Austin TX, US
David J. Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711129, 711118

Abstract:

A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

US Patent:

6981072, Dec 27, 2005

Filed:

Jun 5, 2003

Appl. No.:

10/455169

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F013/00

US Classification:

710 22, 710308, 711200, 711100

Abstract:

A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.

US Patent:

7089373, Aug 8, 2006

Filed:

Jun 12, 2003

Appl. No.:

10/460423

Inventors:

Michael Norman Day - Round Rock TX, US
Roy Moonseuk Kim - Austin TX, US
Mark Richard Nutter - Austin TX, US
Yasukichi Okawa - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711145, 711152

Abstract:

A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

US Patent:

7093080, Aug 15, 2006

Filed:

Oct 9, 2003

Appl. No.:

10/682386

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David J. Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711145, 711202

Abstract:

Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

US Patent:

7103748, Sep 5, 2006

Filed:

Dec 12, 2002

Appl. No.:

10/318541

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/12

US Classification:

711207, 711202, 711203, 711206, 711159

Abstract:

Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

US Patent:

7114035, Sep 26, 2006

Filed:

Sep 4, 2003

Appl. No.:

10/655365

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US
Takeshi Yamazaki - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133

Abstract:

The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

US Patent:

7114042, Sep 26, 2006

Filed:

May 22, 2003

Appl. No.:

10/443727

Inventors:

Michael Norman Day - Round Rock TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

711152, 711711, 711163

Abstract:

The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.