Michael Dale Day

Address:

3836 Mockingbird Ln, Dallas, TX 75205

VIN:

JN1CV6AP8AM400320

Make:

INFINITI

Model:

G37 SEDAN

Year:

2010

US Patent:

6452789, Sep 17, 2002

Filed:

Apr 29, 2000

Appl. No.:

09/562593

Inventors:

Lisa Heid Pallotti - Plano TX
Eric C. Peterson - McKinney TX
Christian L Belady - McKinney TX
Terrel L. Morris - Garland TX
Michael C. Day - Allen TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

361683, 361727, 361788, 395401, 174158 R

Abstract:

The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.

US Patent:

6596948, Jul 22, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/560794

Inventors:

Stuart C. Haden - Lucas TX
Shaun L. Harris - McKinney TX
Michael C. Day - Allen TX
Lisa Heid Pallotti - Plano TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01R 1204

US Classification:

174262, 174260, 174255

Abstract:

A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.

US Patent:

6818835, Nov 16, 2004

Filed:

Apr 22, 2003

Appl. No.:

10/420572

Inventors:

Stuart C. Haden - Lucas TX
Shaun L. Harris - McKinney TX
Michael C. Day - Allen TX
Christian L Belady - McKinney TX
Lisa Heid Pallotti - Plano TX
Paul T. Artman - Dallas TX
Eric C. Peterson - McKinney TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H05K 103

US Classification:

174255, 174261

Abstract:

A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

US Patent:

6820143, Nov 16, 2004

Filed:

Dec 17, 2002

Appl. No.:

10/322127

Inventors:

Michael Norman Day - Round Rock TX
Charles Ray Johns - Austin TX
James Allan Kahle - Austin TX
Peichun Peter Liu - Austin TX
David Shippy - Austin TX
Thuong Quang Truong - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 27, 712 32, 712 33

Abstract:

A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

US Patent:

6961820, Nov 1, 2005

Filed:

Feb 12, 2003

Appl. No.:

10/366440

Inventors:

Michael Norman Day - Round Rock TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
Peichun Peter Liu - Austin TX, US
David J. Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711129, 711118

Abstract:

A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

US Patent:

6981072, Dec 27, 2005

Filed:

Jun 5, 2003

Appl. No.:

10/455169

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F013/00

US Classification:

710 22, 710308, 711200, 711100

Abstract:

A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.

US Patent:

7089373, Aug 8, 2006

Filed:

Jun 12, 2003

Appl. No.:

10/460423

Inventors:

Michael Norman Day - Round Rock TX, US
Roy Moonseuk Kim - Austin TX, US
Mark Richard Nutter - Austin TX, US
Yasukichi Okawa - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711145, 711152

Abstract:

A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

US Patent:

7093080, Aug 15, 2006

Filed:

Oct 9, 2003

Appl. No.:

10/682386

Inventors:

Michael Norman Day - Round Rock TX, US
Harm Peter Hofstee - Austin TX, US
Charles Ray Johns - Austin TX, US
James Allan Kahle - Austin TX, US
David J. Shippy - Austin TX, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711145, 711202

Abstract:

Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.