Michael Alan Duffy

US Patent:

6385265, May 7, 2002

Filed:

Aug 4, 1998

Appl. No.:

09/128901

Inventors:

Michael L. Duffy - Austin TX
Bertrand J. Williams - Austin TX
Phillip J. Kruczkowski - Austin TX
Jaideep Prakash - Austin TX
Nathan Y. Moyal - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03D 324

US Classification:

375374, 327148, 327150

Abstract:

A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

US Patent:

6513127, Jan 28, 2003

Filed:

Sep 24, 1999

Appl. No.:

09/405626

Inventors:

Michael L. Duffy - Austin TX
James H. Jones - Granger TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 106

US Classification:

713501, 370431, 370464

Abstract:

An apparatus comprising a first circuit configured to present one or more control indication signals and (ii) a control clock signal in response to (i) one or more select signals, (ii) one or more clock signals and (iii) one or more divider control signals. The first circuit may be configured to select an active channel from a plurality of channels in response to the one or more select signals.

US Patent:

6535527, Mar 18, 2003

Filed:

Apr 29, 1999

Appl. No.:

09/302193

Inventors:

Michael L. Duffy - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04J 306

US Classification:

370509, 370366, 370545, 370914, 375376, 341101

Abstract:

An apparatus comprising a first circuit, a deserializer circuit and a framer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may comprise (a) a parallel register bank configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals and (b) a state machine configured to generate the one or more select signals in response to one or more control signals. The framer circuit may be configured to generate the one or more control signals in response to (i) one or more input control signals and (ii) the output signal.

US Patent:

6560306, May 6, 2003

Filed:

Dec 17, 1999

Appl. No.:

09/465565

Inventors:

Michael L. Duffy - Austin TX
Mohammad J. Navabi - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03D 324

US Classification:

375376, 375374, 375375, 327147, 327148

Abstract:

A parallel sampling phase detector with linear output response. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five âwindowâ intervals. The âwindowâ intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith.

US Patent:

6665360, Dec 16, 2003

Filed:

Dec 20, 1999

Appl. No.:

09/466652

Inventors:

Michael L. Duffy - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04B 138

US Classification:

375354, 375220

Abstract:

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) a first control signal, (ii) a second control signal, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal. The second circuit may be configured to generate one or more intermediate data signals operating at a second speed in response to (i) the first control signal, (ii) the one or more first clock signals and (iii) the first data signal. The third circuit may be configured to generate an output data signal operating at a third speed in response to (i) the second control signal and (ii) the one or more intermediate data signals.

US Patent:

6839394, Jan 4, 2005

Filed:

Jan 30, 1998

Appl. No.:

09/015989

Inventors:

Michael L. Duffy - Austin TX, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03D 327

US Classification:

375376

Abstract:

A scheme (e. g. , one or more methods, circuits and/or architectures) for detecting the difference in frequencies between two periodic (e. g. , clock) signals and/or for reliably assuring the frequency of an oscillating circuit (e. g. , a voltage controlled oscillator [VCO], a phase locked loop [PLL] containing a VCO, etc. ). The present invention is particularly useful for clock recovery in data communications devices and more particularly in asynchronous transfer mode (ATM) devices, such as SONET/SDH transmitters, receivers and/or transceivers.

US Patent:

8402823, Mar 26, 2013

Filed:

Mar 31, 2011

Appl. No.:

13/077098

Inventors:

Marty Lynn Pflum - Austin TX, US
Michael L. Duffy - Austin TX, US
Douglas S. Piasecki - Austin TX, US
Michael Keith Odland - Austin TX, US

Assignee:

Silicon Laboratories Inc. - Austin TX

International Classification:

G01M 1/00

US Classification:

73462

Abstract:

A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.

US Patent:

8502584, Aug 6, 2013

Filed:

Mar 30, 2012

Appl. No.:

13/436146

Inventors:

Zhiwei Dong - Austin TX, US
Jing Li - Austin TX, US
Michael L. Duffy - Austin TX, US
Michael Mills - Austin TX, US

Assignee:

Silicon Laboratories Inc - Austin TX

International Classification:

H04B 1/38
H04B 1/18

US Classification:

327206, 327205, 375219, 375220, 307109

Abstract:

One aspect of the present invention is directed to a circuit that includes an amplifier circuit disposed between an isolation link and a Schmitt trigger circuit to amplify a differential signal communicated over the isolation link and supply the amplified signal to the Schmitt trigger circuit. In turn, the Schmitt trigger circuit is coupled to the amplifier circuit to receive the differential signal and to supply a differential output signal corresponding to the differential signal communicated over the isolation link.