Michael G Dugan

US Patent:

20180322054, Nov 8, 2018

Filed:

Jul 18, 2018

Appl. No.:

16/038571

Inventors:

- BOISE ID, US
J. MICHAEL ANDREWARTHA - WOODINVILLE WA, US
WILLIAM D. O'LEARY - PLANO TX, US
MICHAEL K. DUGAN - RICHARDSON TX, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 12/0811
G11C 7/10
G06F 12/04
G06F 12/06

Abstract:

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

US Patent:

20180060234, Mar 1, 2018

Filed:

Nov 7, 2017

Appl. No.:

15/806217

Inventors:

- BOISE ID, US
J. Michael Andrewartha - Woodinville WA, US
William D. O'Leary - Plano TX, US
Michael K. Dugan - Richardson TX, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G06F 12/0811
G06F 12/06
G11C 7/10
G06F 12/04

Abstract:

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

US Patent:

20160371185, Dec 22, 2016

Filed:

Sep 1, 2016

Appl. No.:

15/254975

Inventors:

- BOISE ID, US
J. Michael Andrewartha - Woodinville WA, US
William D. O'Leary - Plano TX, US
Michael K. Dugan - Richardson TX, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 12/0811

Abstract:

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.