Michael E Dugan

US Patent:

6564306, May 13, 2003

Filed:

Feb 28, 2001

Appl. No.:

09/797494

Inventors:

Michael K Dugan - Richardson TX
Gary B Gostin - Plano TX
Mark A Heap - Sunnyvale CA
Terry C Huang - San Jose CA
Curtis R. McAllister - Sunnyvale CA
Henry Yu - San Jose CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1212

US Classification:

711155, 711 5, 711141, 714752

Abstract:

An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

US Patent:

6876657, Apr 5, 2005

Filed:

Dec 14, 2000

Appl. No.:

09/737646

Inventors:

Tony M. Brewer - Plano TX, US
Michael K. Dugan - Richardson TX, US
Jim Kleiner - Dallas TX, US
Gregory S. Palmer - Plano TX, US
Paul F. Vogel - Garland TX, US

Assignee:

Chiaro Networks, Ltd. - Richardson TX

International Classification:

H04L012/28

US Classification:

370394, 370401, 370414, 370428

Abstract:

Hardware interconnected around multiple packet forwarding engines prepends sequence numbers to packets going into multiple forwarding engines through parallel paths, After processing by the multiple forwarding engines, packets are reordered using queues and a packet ordering mechanism, such that the sequence numbers are put back into their original prepended order. Exception packets flowing through the forwarding engines do not follow a conventional fast path, but are processed off-line and emerge from the forwarding engines out of order relative to fast path packets. These exception packets are marked, such that after they exit the forwarding engines, they are ordered among themselves independent of conventional fast path packets. Viewed externally, all exception packets are ordered across all multiple forwarding engines independent of the fast path packets.

US Patent:

7366854, Apr 29, 2008

Filed:

May 8, 2003

Appl. No.:

10/434044

Inventors:

John M. Wastlick - Allen TX, US
Michael K. Dugan - Richardson TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711160, 711105

Abstract:

In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.

US Patent:

20080270708, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/741858

Inventors:

Craig Warner - Richardson TX, US
Bryan Hornung - Richardson TX, US
Chris Michael Brueggen - Richardson TX, US
Ryan L. Akkerman - Richardson TX, US
Michael K. Dugan - Richardson TX, US
Gary Gostin - Richardson TX, US
Harvey Ray - Ft. Collins CO, US
Dan Robinson - Richardson TX, US
Christopher Greer - Richardson TX, US

International Classification:

G06F 12/08

US Classification:

711146, 711E12041

Abstract:

A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.

US Patent:

20100036997, Feb 11, 2010

Filed:

Aug 5, 2008

Appl. No.:

12/186372

Inventors:

Tony M. Brewer - Plano TX, US
J. Michael Andrewartha - Plano TX, US
William D. O'Leary - Plano TX, US
Michael K. Dugan - Richardson TX, US

Assignee:

Convey Computer - Richardson TX

International Classification:

G06F 12/06

US Classification:

711 5, 711E12082

Abstract:

The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

US Patent:

20180322054, Nov 8, 2018

Filed:

Jul 18, 2018

Appl. No.:

16/038571

Inventors:

- BOISE ID, US
J. MICHAEL ANDREWARTHA - WOODINVILLE WA, US
WILLIAM D. O'LEARY - PLANO TX, US
MICHAEL K. DUGAN - RICHARDSON TX, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 12/0811
G11C 7/10
G06F 12/04
G06F 12/06

Abstract:

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

US Patent:

20180060234, Mar 1, 2018

Filed:

Nov 7, 2017

Appl. No.:

15/806217

Inventors:

- BOISE ID, US
J. Michael Andrewartha - Woodinville WA, US
William D. O'Leary - Plano TX, US
Michael K. Dugan - Richardson TX, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G06F 12/0811
G06F 12/06
G11C 7/10
G06F 12/04

Abstract:

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

US Patent:

20160371185, Dec 22, 2016

Filed:

Sep 1, 2016

Appl. No.:

15/254975

Inventors:

- BOISE ID, US
J. Michael Andrewartha - Woodinville WA, US
William D. O'Leary - Plano TX, US
Michael K. Dugan - Richardson TX, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 12/0811

Abstract:

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.