Michael Patrick Dugan

US Patent:

6564306, May 13, 2003

Filed:

Feb 28, 2001

Appl. No.:

09/797494

Inventors:

Michael K Dugan - Richardson TX
Gary B Gostin - Plano TX
Mark A Heap - Sunnyvale CA
Terry C Huang - San Jose CA
Curtis R. McAllister - Sunnyvale CA
Henry Yu - San Jose CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1212

US Classification:

711155, 711 5, 711141, 714752

Abstract:

An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

US Patent:

20080270708, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/741858

Inventors:

Craig Warner - Richardson TX, US
Bryan Hornung - Richardson TX, US
Chris Michael Brueggen - Richardson TX, US
Ryan L. Akkerman - Richardson TX, US
Michael K. Dugan - Richardson TX, US
Gary Gostin - Richardson TX, US
Harvey Ray - Ft. Collins CO, US
Dan Robinson - Richardson TX, US
Christopher Greer - Richardson TX, US

International Classification:

G06F 12/08

US Classification:

711146, 711E12041

Abstract:

A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.

Address:

4703 Citation Blvd, Indianapolis, IN 46237

Phone:

(317)7552235

VIN:

2CNALFEC9B6417107

Make:

CHEVROLET

Model:

EQUINOX

Year:

2011