Michael D Erickson

US Patent:

6378084, Apr 23, 2002

Filed:

Mar 29, 1999

Appl. No.:

09/277219

Inventors:

Glenn W. Strunk - Ft. Collins CO
Michael J. Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1100

US Classification:

714 2, 711112

Abstract:

A device and method for enclosure processing of a dual SCSI bus enclosure is described. A single SCSI enclosure processor is provided on an adapter that can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters. The adapters have the ability to automatically configure themselves. In the cluster mode, a first enclosure processor on a first adapter assumes an active status, while a second enclosure processor on a second adapter waits in a standby mode. The standby enclosure processor detects when the active enclosure processor has failed, misoperated, or been removed and automatically failsover, assuming the identity of the active enclosure processor, without disruption to the system. Hot-swapping of the adapter boards is therefore possible.

US Patent:

6408343, Jun 18, 2002

Filed:

Mar 29, 1999

Appl. No.:

09/274385

Inventors:

Michael J. Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO
Glenn W. Strunk - Ft. Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1314

US Classification:

710 15, 710 18, 714 11, 714 25, 714 40, 714 44

Abstract:

A device and method for a peripheral adapter of a dual SCSI bus enclosure is described. An adapter can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters that can be selectively enabled or disabled. The adapters are hot-swappable and have the ability to automatically self configure. In the cluster mode, the adapter supports failover capability from a master adapter to a redundant adapter.

US Patent:

6487624, Nov 26, 2002

Filed:

Aug 13, 1999

Appl. No.:

09/374051

Inventors:

Michael John Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1300

US Classification:

710302, 710 58, 710330, 307 64, 307141

Abstract:

A method and apparatus for hot swapping and bus extension without data corruption. During the hot swapping of a circuit board in a bus, the bus is extended onto or retracted from the circuit board in a manner which does not corrupt the data on the bus. The extension or retraction of the bus is detected and a bus reset is asserted interrupting and preventing transactions on the bus. The bus reset is asserted for a minimum amount of time to allow the bus to stabilize after the hot swap. A bus extension/retraction detection component and a bus reset component perform these functions.

US Patent:

6511198, Jan 28, 2003

Filed:

Dec 22, 1999

Appl. No.:

09/470942

Inventors:

Michael D Erickson - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

F21V 2108

US Classification:

362103, 362 84, 362 85, 313510

Abstract:

The present invention pertains to the provision of Light Emitting Polymer structure, which increases the versatility of the coloring and marking of surface areas of manufactured items, particularly fabric and garments.

US Patent:

6625681, Sep 23, 2003

Filed:

Mar 29, 1999

Appl. No.:

09/272798

Inventors:

Michael John Erickson - Loveland CO
Richard K. Brush - Los Altos CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 3661

US Classification:

710302, 710 58, 710330, 710301, 710303

Abstract:

An apparatus and method for indicating and allowing hot swapping of a circuit board. During both insertion and extraction of a circuit board from a system, two inputs signals are generated from staggered pins located on the circuit boards connector. The inputs are processed through a NAND function implemented with transistors and output to two Schmitt trigger inverters connected in series. The output of the series connection of Schmitt trigger inverters goes high when both input signals are high and goes low when one of the inputs signals goes low. In addition, through the use of a resistor, capacitor combination connected to the input of the first Schmitt trigger inverter, the output signal remains high for a period of time after one of the input signals goes low. This additional period of time prevents any damage or disruption of signaling caused by transient current and voltage fluctuations as a circuit board is inserted or extracted. The output signal can be used in both single-ended and differential SCSI applications.

US Patent:

6629307, Sep 30, 2003

Filed:

Jul 24, 2001

Appl. No.:

09/911997

Inventors:

Michael John Erickson - Loveland CO
Paul J. Mantey - Fort Collins CO
John S Atkinson - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, LP. - Houston TX

International Classification:

G06F 1750

US Classification:

716 15, 716 12, 716 14

Abstract:

The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

US Patent:

6807596, Oct 19, 2004

Filed:

Jul 26, 2001

Appl. No.:

09/916752

Inventors:

Michael John Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO
Bradley D. Winick - Fort Collins CO
Paul J. Mantey - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

710301, 710302, 710 10, 710 16, 714 5, 714 43, 714 44

Abstract:

A system for removal and replacement of core I/O devices while the rest of the computer system is powered-up and operational. The system comprises a custom form-factor core I/O card that contains a plurality of I/O devices, including a processor for managing the cards I/O functions. A command is sent to an operating system, running on a system processor external to the core I/O card, that notifies the system to stop using, and de-configure, the hardware on the core I/O card. Once the OS receives this notification, an indication that the card is ready to be removed is sent to the user. The user then removes the card from its slot and inserts a replacement card into the same slot. The system software then discovers the I/O components on the core I/O card to determine what components are available, and then configures the new I/O device(s).

US Patent:

6883109, Apr 19, 2005

Filed:

Jul 30, 2001

Appl. No.:

09/918030

Inventors:

Michael John Erickson - Loveland CO, US
Edward A Cross - Fort Collins CO, US
David R. Maciorowski - Parker CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F011/00

US Classification:

714 5, 714 16

Abstract:

A method of updating programmable device configuration code stored in EEPROMs of a system is operable on complex systems having separate management and system processors. The method includes executing a sequence for updating programmable device configuration code on a management processor of the system including erasing the EEPROMs, writing at least one block of configuration code to the EEPROMs, and checking for errors after writing. The errors checked for include failure of a FIFO to empty. Upon detecting errors, the method includes automatically retrying writes. Embodiments of the method are operable on systems having multiple serial busses interconnecting EEPROMs to a common configuration logic, and on systems having multiple management processors each capable of accessing the common configuration logic.

Address:

5381 Bear Run Rd, Lakeside, AZ 85929

VIN:

1FTPW14V07FB48441

Make:

FORD

Model:

F-150

Year:

2007