Michael A Field

US Patent:

7065629, Jun 20, 2006

Filed:

Nov 18, 2002

Appl. No.:

10/298983

Inventors:

Andreas Warloe - Fountain Valley CA, US
Michael J. Field - Huntington Beach CA, US

Assignee:

RF Micro Devices, Inc. - Greensboro NC

International Classification:

G06F 12/00

US Classification:

711202, 3423571, 34235712, 34235715, 375150

Abstract:

The address translation logic of the present invention is incorporated in a global positioning system (GPS) receiver and operates to group data in memory based on translating the address from a direct memory access controller. The data includes post-correlated samples of the correlation of a signal with a generated frequency and a generated code having a plurality of time offsets. In general, the address translation logic organizes the data such that each element of the data associated with particular ones of the plurality of time offsets are grouped together in order to improve the efficiency of performing a fast Fourier transform of the data. In addition, the address translation logic allows the transfer of data from correlation circuitry to memory, from the memory to an FFT module, and from the FFT module to the memory using standard DMA controllers.