Michael Patrick Flynn

US Patent:

61753238, Jan 16, 2001

Filed:

Aug 13, 1998

Appl. No.:

9/133895

Inventors:

Michael P. Flynn - Washington MI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 112

US Classification:

341156

Abstract:

A current folding and interpolating circuit (80) in an analog-to-digital converter (10, 152) has L folders, each of them includes M differential pairs (82, 84), each having N first transistors (86-89, 100-103) biased by an input voltage and N second transistors (90-93, 96-99) biased by a reference voltage, and a current source (110, 112) coupled to the source terminals of the first and second transistors. The second transistors of different differential pairs are biased with different reference voltages. Selected drain terminals of the first transistors (89) of one folder (82) are coupled to selected drain terminals of the first transistors (100) of at least one other folder (84), and selected drain terminals of the second transistors (93) of one folder (82) are coupled to selected drain terminals of the second transistors (96) of at least one other folder (84). More than one interpolated signals may be generated between two folders.

US Patent:

61148822, Sep 5, 2000

Filed:

Aug 13, 1998

Appl. No.:

9/133896

Inventors:

Michael P. Flynn - Washington MI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 522

US Classification:

327103

Abstract:

A comparator (20, 30) for comparing first and second current inputs includes a first stage that has a first resistor (43) being coupled to a first input node and operable to produce the a first voltage level corresponding to the first current input at a first voltage node when a CLK signal is high. A second resistor (45) is provided and is coupled to a second input node and operable to produce a second voltage level corresponding to the second current input at a second voltage node when the CLK signal is high. A pair of cross-coupled transistors (36, 37) are coupled to the first and second voltage nodes when a CLK signal is high and are operable to latch the first and second voltage levels when the CLK signal is high. A first differential amplifier (60) is coupled to the first voltage node and is operable to receive the latched first voltage level at a non-inverting input and the latched second voltage level at an inverting, input and to generate a first amplified voltage level when the CLK signal is high. A second differential amplifier (62) is coupled to the second voltage node and is operable to receive the latched first voltage level at an inverting input and the latched second voltage level at a non-inverting input and to generate a second amplified voltage level when the CLK signal is high.