Michael L Frank

US Patent:

6452370, Sep 17, 2002

Filed:

Nov 13, 2001

Appl. No.:

10/010359

Inventors:

Michael L. Frank - Los Gatos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G05F 316

US Classification:

323315, 327537

Abstract:

The present invention provides gate bias to an enhancement mode field effect transistor.

US Patent:

6489862, Dec 3, 2002

Filed:

Oct 3, 2000

Appl. No.:

09/678954

Inventors:

Michael L. Frank - Los Gatos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03F 368

US Classification:

333187, 330302, 330306, 330310, 333189, 455 78

Abstract:

Receive band filtering between the last two stages of an N-stage power amplifier can reduce the R band noise. There are N-1 interstage matching networks interposing N stage amplifiers, where N 2. The interstage matching networks and stage amplifiers are electrically connected in series. The N-1 interstage matching network includes a receive band reject filter positioned proximate to the output of the N-1 stage power amplifier.

US Patent:

6542055, Apr 1, 2003

Filed:

Oct 31, 2000

Appl. No.:

09/704201

Inventors:

Michael L. Frank - Los Gatos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03H 958

US Classification:

333189, 333187, 333190

Abstract:

In one embodiment, an N-stage ladder circuit is serially connected to a bridge (lattice circuit. The N-stage ladder circuit receives differential inputs, e. g. mixers, while the bridge lattice circuit outputs a singled end output, e. g. amplifier. In another embodiment, a bridge lattice circuit is serially connected to an N-stage ladder circuit. The bridge lattice circuit receives a single ended load while the N-stage ladder circuit provides a differential output. Film bulk acoustic resonators are used in the combination ladder and lattice structure for both embodiments to provide the necessary band-pass functionality as well as make the necessary transition from differential to single ended load.

US Patent:

6600390, Jul 29, 2003

Filed:

Dec 13, 2001

Appl. No.:

10/017605

Inventors:

Michael Louis Frank - Los Gatos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03H 954

US Classification:

333189, 333190, 333193

Abstract:

A differential filter includes a first input, a second input, a first output, a second output, and a plurality of acoustic resonator elements. The plurality of acoustic resonator elements is connected to the first input, the second input, the first output and the second output. The acoustic resonator elements are arranged to form at least two of a lattice structure, a full ladder structure and a paired half ladder structure.

US Patent:

6606002, Aug 12, 2003

Filed:

Mar 7, 2002

Appl. No.:

10/092760

Inventors:

Michael Wendell Vice - El Granada CA
Michael Louis Frank - Los Gatos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03F 304

US Classification:

330301, 330302

Abstract:

An amplifier circuit includes an amplifier stage and a balun stage. The amplifier stage includes a common node connected to an external ground. An inductance is located between the common node and the external ground. The balun stage is connected to the amplifier stage. The balun stage includes a balun tail. The balun tail is directly connected to the common node of the amplifier stage so that a resulting connection between the balun tail and the common node bypasses the inductance between the common node and the external ground.

US Patent:

6621490, Sep 16, 2003

Filed:

Mar 3, 2000

Appl. No.:

09/518444

Inventors:

Michael Frank - Sunnyvale CA
Biljana Simsic - Sunnyvale CA

Assignee:

ATI International, SRL - Barbados

International Classification:

G06T 100

US Classification:

345418, 345503, 345522

Abstract:

A method and apparatus for motion compensation using a hardware-assisted abstraction layer is provided. A translator is added in the form of a set-up engine to convert graphics commands to a data structure compatible with a 3-D engine. By doing so, the 3-D engine may be used to serve the dual purposes of processing multiple types of graphics information, for example, 3-D graphics and MPEG video. As standards change and the 3-D engine is updated to accommodate new types of graphics information, the set-up engine may be modified to support the updated 3-D engine without requiring changes to drivers controlled by other entities.

US Patent:

6674441, Jan 6, 2004

Filed:

Jul 26, 2000

Appl. No.:

09/625581

Inventors:

Michael Frank - Sunnyvale CA

Assignee:

ATI International, SRL - Barbados

International Classification:

G06F 1516

US Classification:

345503, 345519, 345520, 711206, 711207

Abstract:

A method and apparatus for improving performance of an AGP device is provided. In one embodiment of the invention, a second-level cache is provided for a TLB, and part of the data or part of the address that is not otherwise used for determining a TLB entry is divided by a prime number to determine which TLB entry to allocate. One embodiment of the invention provides the ability to load multiple cache lines during a single memory access without incurring additional transfer, storage, or management complexities. The full number of bits of each memory access may be used to load cache lines. One embodiment of the invention loads multiple cache lines for translations of consecutive ranges of addresses. Since the translations included in the multiple cache lines cover consecutive ranges of addresses, the relationship between the multiple cache lines loaded for a single memory access is understood, and additional complexity for cache management is avoided. Loading of multiple cache lines for translations of consecutive ranges of addresses also improves performance by increasing the number of translations available in the TLB.

US Patent:

6680647, Jan 20, 2004

Filed:

Dec 13, 2001

Appl. No.:

10/020258

Inventors:

Edward Russel Brown - Sunnyvale CA
Michael Louis Frank - Los Gatos CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03F 114

US Classification:

330 51, 330 53, 330150, 330151, 330157, 330124, 330302, 330310

Abstract:

An amplifier and bypass switch circuit includes a circuit input, a circuit output, an amplifier and a switching circuit. The amplifier has an amplifier control input, and a first amplifier output. The amplifier control input is connected to the circuit input. The amplifier output is connected to the circuit output. The switching circuit includes a control input, a switch input, a switch output and a phase matching network. The switch output is connected to the circuit output. The switch input is connected to the circuit input. The phase matching network preserves phase information when the amplifier and bypass switch circuit switches between an amplifier mode and a bypass mode.

Address:

3608 Canopus Ct, Louisville, KY 40219

VIN:

JTDBT923871139891

Make:

TOYOTA

Model:

YARIS

Year:

2007