Michael J Golden

US Patent:

7257678, Aug 14, 2007

Filed:

Oct 1, 2004

Appl. No.:

10/956560

Inventors:

Michael L. Golden - Santa Clara CA, US
Richard E. Klass - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711118, 711100, 711122, 711154

Abstract:

In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.

US Patent:

7472224, Dec 30, 2008

Filed:

Oct 1, 2004

Appl. No.:

10/956561

Inventors:

Richard E. Klass - San Jose CA, US
Michael L. Golden - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711119, 711100, 711118, 711154

Abstract:

In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache memory. The processing node further includes a configuration unit that is coupled to the first processor core and the second processor core. The configuration unit may selectably disable portions of the first and the second cache memories.

US Patent:

20120144393, Jun 7, 2012

Filed:

Dec 1, 2010

Appl. No.:

12/957861

Inventors:

James Vinh - San Jose CA, US
Kyle S. Viau - Fremont CA, US
Michael L. Golden - Mountain View CA, US
Ganesh Venkataramanan - Sunnyvale CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

A method and apparatus for scheduling execution of instructions in a multi-issue processor. The apparatus includes post wake logic circuitry configured to track a plurality of entries corresponding to a plurality of instructions to be scheduled. Each instruction has at least one associated source address and a destination address. The post wake logic circuitry is configured to drive a ready input indicating an entry that is ready for execution based on a current match input. A picker circuitry is configured to pick an instruction for execution based the ready input. A compare circuit is configured to determine the destination address for the picked instruction, compare the destination address to the source address for all entries and drive the current match input.

US Patent:

62783084, Aug 21, 2001

Filed:

Oct 8, 1999

Appl. No.:

9/415760

Inventors:

Hamid Partovi - Sunnyvale CA
Michael Golden - Sunnyvale CA
John Yong - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 312
H03K 3037
H03K 3286
H03K 3356

US Classification:

327218

Abstract:

A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the "output side" and the "reference side," are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i. e. , is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit.

US Patent:

20220413584, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/358709

Inventors:

- Santa Clara CA, US
Gokul Subramani Ramalingam Lakshmi Devi - Santa Clara CA, US
Michael L. Golden - Santa Clara CA, US
Larry D. Hewitt - Austin TX, US

International Classification:

G06F 1/3228

Abstract:

Methods and systems for facilitating improved power consumption control of a plurality of processing cores are disclosed. The methods improve the power consumption control by performing power throttling based on a determined excess power consumption. The methods include the steps of: monitoring using at least one event count component in the respective processing core a plurality of distributed events; calculating an accumulated weighted sum of the distributed events from the event count component; determining an excess power consumption by comparing the accumulated weighted sum with a threshold power value; and adjusting power consumption of the respective processing core based on the determined excess power consumption.

US Patent:

20230032375, Feb 2, 2023

Filed:

Jul 30, 2021

Appl. No.:

17/390293

Inventors:

- Santa Clara CA, US
Michael L. Golden - Santa Clara CA, US
Sean M. O'Mullan - Austin TX, US
James Wingfield - Austin TX, US
Keith A. Kasprak - Austin TX, US
Russell Schreiber - Austin TX, US
Michael Estlick - Fort Collins CO, US

International Classification:

G06F 11/14
G06F 11/07
G06F 9/30
G06F 9/50

Abstract:

An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of undefective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

US Patent:

20210056031, Feb 25, 2021

Filed:

Nov 6, 2020

Appl. No.:

17/091993

Inventors:

- Santa Clara CA, US
Michael L. GOLDEN - Santa Clara CA, US
Marius EVERS - Santa Clara CA, US

International Classification:

G06F 12/0862
G06F 12/128
G06F 12/1027
G06F 1/3234
G06F 12/0815
G06F 12/1009
G06F 12/0811

Abstract:

A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

US Patent:

20190129853, May 2, 2019

Filed:

Nov 1, 2017

Appl. No.:

15/800727

Inventors:

- Sunnyvale CA, US
Michael L. GOLDEN - Sunnyvale CA, US
Marius EVERS - Sunnyvale CA, US

International Classification:

G06F 12/0862
G06F 12/128
G06F 12/1027
G06F 1/32
G06F 12/0811
G06F 12/0815
G06F 12/1009

Abstract:

A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.