Michael D Hammer

US Patent:

6938197, Aug 30, 2005

Filed:

Aug 1, 2002

Appl. No.:

10/210367

Inventors:

James A. Doubler - Wheaton IL, US
Michael P. Hammer - Westchester IL, US
Shu C. Yuan - Naperville IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03M013/00
G06F011/10

US Classification:

714757, 714807

Abstract:

The present invention provides a cyclic redundancy check (CRC) calculation system for a packet arriving on an n-byte wide bus. In one embodiment, the system includes a bus-wide CRC subsystem configured to calculate an intermediate CRC value based on complete segments of the packet. In addition, the system includes a byte-wide CRC subsystem, coupled to the bus-wide subsystem, configured to calculate a remaining CRC value based on the intermediate CRC value and one or more bytes within an incomplete segment of the packet on a byte by byte basis. In addition, a method of calculating a CRC value for a packet arriving on a n-byte wide bus and a data transmission system incorporating the system are also disclosed.

US Patent:

7536615, May 19, 2009

Filed:

Mar 26, 2007

Appl. No.:

11/691003

Inventors:

David Pierce - Wheaton IL, US
Michael Hammer - Westchester IL, US
Brian M. Caslis - Wilsonville OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 31/28

US Classification:

714725, 714 37, 714 39, 714 45, 714724, 714732, 714742, 716 4, 716 16, 716 17, 716 18, 326 37, 326 38, 326 39, 703 28

Abstract:

A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.

US Patent:

7606851, Oct 20, 2009

Filed:

Aug 10, 2005

Appl. No.:

11/202149

Inventors:

David Pierce - Wheaton IL, US
Michael Hammer - Westchester IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 17/15

US Classification:

708422

Abstract:

In one embodiment of the invention, a circuit may include and/or involve a correlator, a programmable fabric, and logic to enable selection of one of default processing logic and alternate processing logic to process corresponding data and coefficient values of the correlator.

US Patent:

7743296, Jun 22, 2010

Filed:

Mar 26, 2007

Appl. No.:

11/691040

Inventors:

David Pierce - Wheaton IL, US
Michael Hammer - Westchester IL, US
Brian M. Caslis - Wilsonville OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 31/28
G06F 11/00
G06F 9/455
G06F 7/38
G06F 17/50
G06F 9/45
H03K 17/693
H03K 19/177
H03K 19/173
H03K 19/00

US Classification:

714725, 714 37, 714 39, 714 45, 714724, 714732, 714742, 716 4, 716 16, 716 17, 716 18, 326 37, 326 38, 326 39, 703 28

Abstract:

A method of programming a programmable logic device (PLD), in accordance with an embodiment, includes receiving trigger unit information of a logic analyzer via a software interface for monitoring internal PLD signals and providing trigger unit output signals based on the internal PLD signals for the corresponding trigger units; and receiving trigger expression information of the logic analyzer via the software interface as a text string of logic operators and operands, wherein the operands represent the trigger unit output signals. The method may further include generating configuration data based on the trigger unit information and the trigger expression information; and providing the configuration data to the PLD, wherein a trigger expression based on the trigger expression information is stored within memory of the PLD.

US Patent:

7924054, Apr 12, 2011

Filed:

Feb 16, 2010

Appl. No.:

12/706227

Inventors:

James Doubler - Wheaton IL, US
Michael Hammer - Westchester IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 93

Abstract:

A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

US Patent:

8138790, Mar 20, 2012

Filed:

Apr 11, 2011

Appl. No.:

13/083889

Inventors:

James Doubler - Wheaton IL, US
Michael Hammer - Westchester IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 93

Abstract:

In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

US Patent:

8165164, Apr 24, 2012

Filed:

Jun 30, 2009

Appl. No.:

12/494822

Inventors:

Michael Hammer - Westchester IL, US
David Pierce - Wheaton IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H04J 3/24

US Classification:

370474, 370535

Abstract:

A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first data words. The mapping and de-mapping is responsive to address signals that may be stored in a memory such that a desired mapping or de-mapping corresponds to a particular programming of the memory. In this fashion, the mapping and de-mapping is in-system reconfigurable.

US Patent:

8495264, Jul 23, 2013

Filed:

Jul 8, 2011

Appl. No.:

13/178536

Inventors:

Michael Hammer - Westchester IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 13/12
H04L 7/00

US Classification:

710 71, 375354

Abstract:

Parallel data generated by demultiplexing received serial data such as in a Serial RapidIO (SRIO) data stream can become misaligned as a result of, e. g. , clock tolerance compensation (CTC) processing at the receiver. In one embodiment of the invention, the misaligned parallel data is properly aligned based on a mapping from each of a finite number of possible previous alignment conditions (e. g. , words A-D) to a corresponding finite number of possible subsequent alignment conditions (e. g. , words B-G). The change from a previous alignment condition to a different subsequent alignment condition is recognized by determining the location of start-of-packet (SOP) or start-of-control-symbol (SOC) data in the parallel data stream.