Michael Han

US Patent:

20140008788, Jan 9, 2014

Filed:

Feb 26, 2013

Appl. No.:

13/777271

Inventors:

Lily Zhao - San Diego CA, US
Michael Han - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H01L 23/00

US Classification:

257737, 438613, 438106

Abstract:

Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

US Patent:

61669512, Dec 26, 2000

Filed:

Aug 6, 1999

Appl. No.:

9/370010

Inventors:

Narbeh Derhacobian - Belmont CA
Hao Fang - Cupertino CA
Michael Han - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518503

Abstract:

A method and circuit for sensing multi states of a NAND memory cell by applying reverse bias voltage at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the applied reverse P well bias, and sensing the memory cell state.

US Patent:

61886068, Feb 13, 2001

Filed:

Aug 6, 1999

Appl. No.:

9/369600

Inventors:

Narbeh Derhacobian - Belmont CA
Hao Fang - Cupertino CA
Michael Han - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518517

Abstract:

A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.

US Patent:

20140124877, May 8, 2014

Filed:

Feb 11, 2013

Appl. No.:

13/764261

Inventors:

- San Diego CA, US
Lily Zhao - San Diego CA, US
Michael Han - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H01L 29/43
H01L 29/84
H01L 21/768
H01L 23/498

US Classification:

257415, 257737, 438622

Abstract:

A conductive interconnect includes an inorganic collar. The conductive interconnect includes a conductive support layer. The conductive interconnect also includes a conductive material on the conductive support layer. The conductive interconnect further includes an inorganic collar partially surrounding the conductive material. The inorganic collar is also disposed on sidewalls of the conductive support layer.