Michael K Han

US Patent:

6344994, Feb 5, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795849

Inventors:

Darlene G. Hamilton - San Jose CA
Yider Wu - Campbell CA
Michael Han - San Jose CA

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518505, 36518511, 257316

Abstract:

Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can be positioned between the blocks. Alternatively, the wordline width for the last block or sector wordline can be changed or different nitride used with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.

US Patent:

6567303, May 20, 2003

Filed:

Jan 16, 2002

Appl. No.:

10/050483

Inventors:

Darlene G. Hamilton - San Jose CA
Narbeh Derhacobian - Belmont CA
Tim Thurgate - Sunnyvale CA
Michael K. Han - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518503, 36518518, 36518522, 36518529

Abstract:

A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

US Patent:

6529410, Mar 4, 2003

Filed:

Sep 20, 2000

Appl. No.:

09/665916

Inventors:

Michael Han - San Jose CA
Narbeh Derhacobian - Belmont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518517, 36518518, 36518528, 257347

Abstract:

An efficient NAND array structure includes memory cells coupled in series between a bit-line and a select source transistor, without a select drain transistor. The memory cells each include a floating gate transistor, having a control gate connected to a word-line, which selects the memory cell during its programming. In one embodiment, the NAND array structure includes a buried layer at a junction between the substrate and a well in which the memory cells are formed. Programming is achieved using hot electron injection. In one embodiment, multiple memory cells are programmed simultaneously.

US Patent:

20040249643, Dec 9, 2004

Filed:

Jun 6, 2003

Appl. No.:

10/455378

Inventors:

Lien Ouyang - Los Altos CA, US
Michael Han - San Jose CA, US
Abraham Ma - Fremont CA, US

Assignee:

MA LABORATORIES, INC.

International Classification:

G06F017/60

US Classification:

705/001000, 705/400000

Abstract:

A method utilizes a keyword based rule set to crawl through the web pages and fetch the related product prices. There are many algorithms involved for accurately matching and selecting the required items. The data is then sorted by the price and brand and compared with the database of a group of known products. The prices of the known products are then adjusted via a set of built-in rules to put them in a very competitive position, such as number 1 or 2 among the same product category. The new prices make the seller's products very competitive online. The new price list will then automatically be posted to the web server to replace the old prices. The whole process is automated by simply placing the program on a computer operating system scheduler and let it run periodically according to the specified date and time.

US Patent:

20140008788, Jan 9, 2014

Filed:

Feb 26, 2013

Appl. No.:

13/777271

Inventors:

Lily Zhao - San Diego CA, US
Michael Han - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H01L 23/00

US Classification:

257737, 438613, 438106

Abstract:

Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

US Patent:

61669512, Dec 26, 2000

Filed:

Aug 6, 1999

Appl. No.:

9/370010

Inventors:

Narbeh Derhacobian - Belmont CA
Hao Fang - Cupertino CA
Michael Han - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518503

Abstract:

A method and circuit for sensing multi states of a NAND memory cell by applying reverse bias voltage at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the applied reverse P well bias, and sensing the memory cell state.

US Patent:

61886068, Feb 13, 2001

Filed:

Aug 6, 1999

Appl. No.:

9/369600

Inventors:

Narbeh Derhacobian - Belmont CA
Hao Fang - Cupertino CA
Michael Han - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518517

Abstract:

A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.

US Patent:

20190220886, Jul 18, 2019

Filed:

Jan 12, 2018

Appl. No.:

15/870042

Inventors:

Michael Han - Morgan Hill CA, US

International Classification:

G06Q 30/02

Abstract:

A computerized process can be used to create and distribute a durable coupon token redeemable with a company agreeing to permit a user redeem the durable coupon token for a discount. The process includes, within a computerized processor, operating programming configured to create the durable coupon token. The durable coupon token includes a digital security key associated with the durable coupon token configured to provide transferrable ownership of the durable coupon token. The process further includes distributing the durable coupon token to a consumer. The durable coupon token is configured to enable the consumer to claim the discount with the company.