Michael A Hargrove

US Patent:

8076209, Dec 13, 2011

Filed:

Apr 30, 2010

Appl. No.:

12/771948

Inventors:

Frank Bin Yang - Mahwah NJ, US
Rohit Pal - Fishkill NY, US
Michael J. Hargrove - Clinton Corners NY, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438299, 438269, 438369, 257288, 257369

Abstract:

Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

US Patent:

8294211, Oct 23, 2012

Filed:

Jan 14, 2010

Appl. No.:

12/687610

Inventors:

Bin Yang - Mahwah NJ, US
Rohit Pal - Clifton Park NY, US
Michael Hargrove - Clinton Corners NY, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 29/786

US Classification:

257347, 257E21704, 257E27112, 257E29275, 438151

Abstract:

A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

US Patent:

7994014, Aug 9, 2011

Filed:

Oct 10, 2008

Appl. No.:

12/249570

Inventors:

Frank Bin Yang - Mahwah NJ, US
Rohit Pal - Fishkill NY, US
Michael J. Hargrove - Clinton Corners NY, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438300, 257E21619, 257E21634

Abstract:

The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

US Patent:

20080258225, Oct 23, 2008

Filed:

Apr 20, 2007

Appl. No.:

11/738135

Inventors:

Frank (Bin) YANG - Mahwah NJ, US
Michael HARGROVE - Clinton Corners NY, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Austin TX

International Classification:

H01L 29/94
H01L 21/4763

US Classification:

257364, 438595, 257E21495, 257E29345

Abstract:

MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a low interface trap density between the offset spacer and the semiconductor substrate. First ions of a conductivity-determining impurity type are implanted into the semiconductor substrate using the gate stack and the offset spacer as an implantation mask to form spaced-apart impurity-doped extensions.

US Patent:

20100012988, Jan 21, 2010

Filed:

Jul 21, 2008

Appl. No.:

12/176916

Inventors:

Frank Bin YANG - Mahwah NJ, US
Michael J. HARGROVE - Clinton Corners NY, US
Rohit PAL - Fishkill NY, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 29/00
H01L 21/8236

US Classification:

257288, 438278, 257E21631, 257E29001

Abstract:

Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.

US Patent:

20110169083, Jul 14, 2011

Filed:

Jan 14, 2010

Appl. No.:

12/687607

Inventors:

Bin YANG - Mahwah NJ, US
Rohit PAL - Mahwah NJ, US
Michael HARGROVE - Clinton Corners NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 29/786
H01L 21/86

US Classification:

257347, 438151, 257E29275, 257E29273, 257E21411, 257E21704

Abstract:

A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

US Patent:

20110254092, Oct 20, 2011

Filed:

Apr 14, 2010

Appl. No.:

12/759969

Inventors:

Bin Yang - Mahwah NJ, US
Michael Hargrove - Clinton Corners NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 27/092
H01L 21/31

US Classification:

257351, 438761, 257E27062, 257E2124

Abstract:

A semiconductor is formed on an ETSOI layer, the thin Si layer of an ETSOI substrate, with enhanced channel stress. Embodiments include semiconductor devices having dual stress liners on the back surface of the ETSOI layer. An embodiment includes forming an ETSOI substrate comprising an extra thin layer of Si on a backside substrate with an insulating layer, e.g., a BOX, there between, forming a semiconductor device on the Si surface, removing the backside substrate, as by CMP and the insulting layer, as by wet etching, and forming a stress liner on the backside of the remaining Si layer opposite the semiconductor device. The use of stress liners on the backside of the ETSOI layer enhances channel stress without modifying ETSOI semiconductor process flow.