Michael J Hargrove

US Patent:

6335262, Jan 1, 2002

Filed:

Jan 14, 1999

Appl. No.:

09/231617

Inventors:

Scott W. Crowder - Ossining NY
Anthony Gene Domenicucci - Hopewell Junction NY
Liang-Kai Han - Fishkill NY
Michael John Hargrove - Clinton Corners NY
Paul Andrew Ronsheim - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2131

US Classification:

438440, 438528, 438981, 438275, 148DIG 116, 148DIG 163

Abstract:

A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions. The growth rate of the silicon dioxide will be slower in the areas containing the nitrogen ions and therefore the silicon dioxide layer will be thinner in those regions as compared to the silicon dioxide layer in the regions not containing the nitrogen ions. Also provided are structures obtained by the above process.

US Patent:

6344671, Feb 5, 2002

Filed:

Dec 14, 1999

Appl. No.:

09/460885

Inventors:

Jack A. Mandelman - Stormville NY
Fariborz Assaderaghi - Mahopac NY
Michael J. Hargrove - Clinton Corners NY
Peter Smeys - White Plains NY
Norman J. Rohrer - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27108

US Classification:

257296, 257347, 257901, 257908

Abstract:

A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions.

US Patent:

6369434, Apr 9, 2002

Filed:

Jul 30, 1999

Appl. No.:

09/363742

Inventors:

Kai Chen - Hopewell Junction NY
Scott W. Crowder - Ossining NY
Liang-Kai Han - Fishkill NY
Michael J. Hargrove - Clinton Corners NY
Kam-Leung Lee - Putnam Valley NY
Hung Y. Ng - New Milford NJ

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257402, 257610

Abstract:

A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.

US Patent:

6372559, Apr 16, 2002

Filed:

Nov 9, 2000

Appl. No.:

09/709073

Inventors:

Scott Crowder - Ossining NY
Michael J. Hargrove - Clinton Corners NY
Suk Hoon Ku - Beacon NY
L. Ronald Logan - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438157, 438156, 438162, 438166

Abstract:

A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.

US Patent:

6426244, Jul 30, 2002

Filed:

Jul 12, 2001

Appl. No.:

09/903820

Inventors:

Michael J. Hargrove - Clinton Corners NY
Mario M. Pelella - Gainesville FL
Steven H. Voldman - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438149, 438155, 438164, 438197, 438200, 438151, 257347, 257352, 257353, 257355

Abstract:

A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate s formed during the BEOL process. The transistor may by a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

US Patent:

6433587, Aug 13, 2002

Filed:

Mar 17, 2000

Appl. No.:

09/528207

Inventors:

Fariborz Assaderaghi - Mahopac NY
Kerry Bernstein - Underhill NY
Michael J. Hargrove - Clinton Corners NY
Norman J. Rohrer - Underhill VT
Peter Smeys - White Plaines NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096

US Classification:

326 95, 326 98

Abstract:

A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.

US Patent:

6531375, Mar 11, 2003

Filed:

Sep 18, 2001

Appl. No.:

09/955375

Inventors:

Kenneth J. Giewont - Hopewell Junction NY
Eric Adler - Jericho VT
Neena Garg - Fishkill NY
Michael J. Hargrove - Clinton Corners NY
Junedong Lee - Hopewell Junction NY
Dominic J. Schepis - Wappingers Falls NY
Isabel Ying Yang - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

438407, 438423, 438480

Abstract:

A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e. g. O implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a âtouch-upâ O implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the âtouch-upâ O implant (second ion implant), which in turn would result in a leaky BOX.

US Patent:

6531741, Mar 11, 2003

Filed:

Mar 3, 1999

Appl. No.:

09/261333

Inventors:

Michael J. Hargrove - Clinton Corners NY
Steven H. Voldman - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265

US Classification:

257350, 257349

Abstract:

An SOI structure with a dual thickness buried insulating layer and method of forming the same is provided. A first substrate has raised portions each with a planar top surface. A dielectric layer covers the first substrate and its raised portions. The dielectric layer has a planar top surface. A second substrate layer is formed on the planar top surface of the dielectric layer. Semiconductor elements may be formed in the second substrate layer. The semiconductor elements pertain to core circuit elements, peripheral circuits, and electrostatic discharge (EDS) circuits.