Michael F Hargrove

US Patent:

6335262, Jan 1, 2002

Filed:

Jan 14, 1999

Appl. No.:

09/231617

Inventors:

Scott W. Crowder - Ossining NY
Anthony Gene Domenicucci - Hopewell Junction NY
Liang-Kai Han - Fishkill NY
Michael John Hargrove - Clinton Corners NY
Paul Andrew Ronsheim - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2131

US Classification:

438440, 438528, 438981, 438275, 148DIG 116, 148DIG 163

Abstract:

A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions. The growth rate of the silicon dioxide will be slower in the areas containing the nitrogen ions and therefore the silicon dioxide layer will be thinner in those regions as compared to the silicon dioxide layer in the regions not containing the nitrogen ions. Also provided are structures obtained by the above process.

US Patent:

6372559, Apr 16, 2002

Filed:

Nov 9, 2000

Appl. No.:

09/709073

Inventors:

Scott Crowder - Ossining NY
Michael J. Hargrove - Clinton Corners NY
Suk Hoon Ku - Beacon NY
L. Ronald Logan - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438157, 438156, 438162, 438166

Abstract:

A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.

US Patent:

7183175, Feb 27, 2007

Filed:

Jul 1, 2005

Appl. No.:

11/172707

Inventors:

Steven John Koester - Ossining NY, US
Klaus Dietrich Beyer - Poughkeepsie NY, US
Michael John Hargrove - Clinton Corners NY, US
Kern Rim - Yorktown Heights NY, US
Kevin Kok Chan - Staten Island NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/762

US Classification:

438429, 438435, 257E21546

Abstract:

A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

US Patent:

8076209, Dec 13, 2011

Filed:

Apr 30, 2010

Appl. No.:

12/771948

Inventors:

Frank Bin Yang - Mahwah NJ, US
Rohit Pal - Fishkill NY, US
Michael J. Hargrove - Clinton Corners NY, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438299, 438269, 438369, 257288, 257369

Abstract:

Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

US Patent:

8294211, Oct 23, 2012

Filed:

Jan 14, 2010

Appl. No.:

12/687610

Inventors:

Bin Yang - Mahwah NJ, US
Rohit Pal - Clifton Park NY, US
Michael Hargrove - Clinton Corners NY, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 29/786

US Classification:

257347, 257E21704, 257E27112, 257E29275, 438151

Abstract:

A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

US Patent:

7994014, Aug 9, 2011

Filed:

Oct 10, 2008

Appl. No.:

12/249570

Inventors:

Frank Bin Yang - Mahwah NJ, US
Rohit Pal - Fishkill NY, US
Michael J. Hargrove - Clinton Corners NY, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438300, 257E21619, 257E21634

Abstract:

The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

US Patent:

20030094660, May 22, 2003

Filed:

Oct 3, 2001

Appl. No.:

09/968793

Inventors:

Scott Crowder - Ossining NY, US
Anthony Domenicucci - Hopewell Junction NY, US
Liang-Kai Han - Fishkill NY, US
Michael Hargrove - Clinton Corners NY, US
Paul Ronsheim - Hopewell Junction NY, US

International Classification:

H01L029/94

US Classification:

257/391000

Abstract:

A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions. The growth rate of the silicon dioxide will be slower in the areas containing the nitrogen ions and therefore the silicon dioxide layer will be thinner in those regions as compared to the silicon dioxide layer in the regions not containing the nitrogen ions. Also provided are structures obtained by the above process.

US Patent:

20040164373, Aug 26, 2004

Filed:

Feb 25, 2003

Appl. No.:

10/374866

Inventors:

Steven Koester - Ossining NY, US
Klaus Beyer - Poughkeepsie NY, US
Michael Hargrove - Clinton Corners NY, US
Kern Rim - Yorktown Heights NY, US
Kevin Chan - Staten Island NY, US

International Classification:

H01L021/336
H01L021/76
H01L029/00

US Classification:

257/499000, 438/424000, 438/296000, 257/510000

Abstract:

A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.