Michael Shawn Harper

US Patent:

7515498, Apr 7, 2009

Filed:

Feb 13, 2007

Appl. No.:

11/674227

Inventors:

Robert Christopher Dixon - Austin TX, US
Michael Wayne Harper - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 7/00

US Classification:

3652257, 365 96

Abstract:

A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back again to a virtual blown state. The fuse apparatus includes multiple VEFs, each VEF exhibiting a respective address. The fuse apparatus also includes an address pool including multiple address pool locations. A fuse programmer stores an address of one of the VEFs in one or more address pool locations to indicate one or more state changes for a particular VEF. The fuse programmer may also store different VEF addresses in different address pool locations to indicate state changes for different VEFs.

US Patent:

7737763, Jun 15, 2010

Filed:

Feb 13, 2007

Appl. No.:

11/674238

Inventors:

Robert Christopher Dixon - Austin TX, US
Michael Wayne Harper - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01H 37/76

US Classification:

327525, 326 38, 365 96

Abstract:

A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to a virtual blown state.

US Patent:

8639855, Jan 28, 2014

Filed:

Oct 20, 2008

Appl. No.:

12/254261

Inventors:

Michael W. Harper - Round Rock TX, US
Larry S. Leitner - Austin TX, US
Mack W. Riley - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 5/00
G06F 13/12
G06F 11/00
G11C 29/00
G01R 31/28
G05B 9/02
H01L 29/10
G06F 17/40

US Classification:

710 15, 710 18, 710 36, 710 62, 714 25, 714 45, 714 471, 714723, 714724, 714742, 700 79, 257 48, 702187

Abstract:

Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.

US Patent:

20140053034, Feb 20, 2014

Filed:

Aug 15, 2012

Appl. No.:

13/586227

Inventors:

Michael W. Harper - Round Rock TX, US
Mack W. Riley - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G01R 31/3177

US Classification:

714729, 714733, 714E11155

Abstract:

An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

US Patent:

20230055935, Feb 23, 2023

Filed:

Aug 18, 2021

Appl. No.:

17/405173

Inventors:

- Armonk NY, US
VENKAT HARISH NAMMI - Austin TX, US
DEREJE YILMA - Rochester MN, US
Chad Andrew Marquart - Austin TX, US
Glen A. Wiedemeier - Austin TX, US
JEFFREY KWABENA OKYERE - Carrollton TX, US
Erik English - Salt Point NY, US
Christopher Steffen - Rochester MN, US
Vikram B. Raj - Austin TX, US
Michael Wayne Harper - Austin TX, US

International Classification:

G01R 31/3177
G01R 31/317
G06F 1/08

Abstract:

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

US Patent:

20190363813, Nov 28, 2019

Filed:

May 24, 2018

Appl. No.:

15/988869

Inventors:

- Armonk NY, US
Michael W. HARPER - Round Rock TX, US
Mack W. RILEY - Austin TX, US
Michael B. SPEAR - Round Rock TX, US

International Classification:

H04J 3/06
H04B 17/29
H04L 7/04

Abstract:

Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.

US Patent:

20150061278, Mar 5, 2015

Filed:

Aug 30, 2013

Appl. No.:

14/015410

Inventors:

- Armonk NY, US
Michael W. Harper - Round Rock TX, US
Ryan M. Kruse - Round Rock TX, US
Arden L. Moore - Cedar Park TX, US
Brian G. Veraa - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B42D 25/36

US Classification:

283 67, 432 92

Abstract:

Some embodiments of the inventive subject matter include a computer program product for validating a test thermoreflective mark. The computer program product can include computer usable program code configured to control a temperature regulation unit configured to govern a temperature of a thermoreflective mark. The computer usable program code can be further configured to control an electromagnetic waver emitter to present at a first temperature, a first electromagnetic wave. The computer usable program code can be further configured to record a first reflective profile. The computer usable program code can be further configured to control the electromagnetic wave emitter to present at a second temperature, a second electromagnetic wave. The computer usable program code can be further configured to record a second reflective profile. The computer usable code can be further configured to validate the thermoreflective mark based on the first reflective profile and the second reflective profile.

US Patent:

20150061279, Mar 5, 2015

Filed:

Dec 11, 2013

Appl. No.:

14/102664

Inventors:

- Armonk NY, US
Michael W. Harper - Round Rock TX, US
Ryan M. Kruse - Round Rock TX, US
Arden L. Moore - Cedar Park TX, US
Brian G. Veraa - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B42D 25/20
B42D 25/36

US Classification:

283 67

Abstract:

An anti-counterfeiting technique presents, to a test thermoreflective mark at a first temperature, a first electromagnetic wave. A first test reflective profile for the test thermoreflective mark associated with the first temperature is recorded. A second electromagnetic wave is presented to the test thermoreflective mark at a second temperature. A second test reflective profile for the test thermoreflective mark associated with the second temperature is recorded. The first test reflective profile is compared with a first control reflective profile that is associated with a genuine thermoreflective mark. The second test reflective profile is compared with a second control reflective profile that is associated with the genuine thermoreflective mark.