Michael Craig Harper

US Patent:

7977248, Jul 12, 2011

Filed:

Dec 31, 2007

Appl. No.:

12/006204

Inventors:

Elliot Tan - Portland OR, US
Michael K. Harper - Hillsboro OR, US
James Jeong - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438717, 438585, 438587, 438399, 438696, 430313, 430311

Abstract:

In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.

US Patent:

8314034, Nov 20, 2012

Filed:

Dec 23, 2010

Appl. No.:

12/978160

Inventors:

Elliot N. Tan - Portland OR, US
Michael K. Harper - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438717, 438734, 438736, 438738, 257E21017, 257E2102

Abstract:

Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.

US Patent:

20210305430, Sep 30, 2021

Filed:

Mar 27, 2020

Appl. No.:

16/833208

Inventors:

- Santa Clara CA, US
Stephen SNYDER - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
William HSU - Hillsboro OR, US
Urusa ALAAN - Hillsboro OR, US
Tahir GHANI - Portland OR, US
Michael K. HARPER - Hillsboro OR, US
Vivek THIRTHA - Portland OR, US
Shu ZHOU - Portland OR, US
Nitesh KUMAR - Beaverton OR, US

International Classification:

H01L 29/78
H01L 29/423
H01L 29/06
H01L 29/165
H01L 29/10
H01L 29/08
H01L 21/02

Abstract:

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

US Patent:

20200403081, Dec 24, 2020

Filed:

Jun 19, 2019

Appl. No.:

16/445700

Inventors:

Seung Hoon Sung - Portland OR, US
Ashish Verma Penumatcha - Hillsboro OR, US
Matthew Metz - Portland OR, US
Michael Harper - Hillsboro OR, US
Jack Kavalieros - Portland OR, US
Uygar Avci - Portland OR, US
Ian Young - Portland OR, US

International Classification:

H01L 29/51
H01L 29/49
H01L 29/423
H01L 29/40

Abstract:

Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).

US Patent:

20170323965, Nov 9, 2017

Filed:

Jul 19, 2017

Appl. No.:

15/654597

Inventors:

- Santa Clara CA, US
Pragyansri PATHI - Portland OR, US
Michael K. HARPER - Hillsboro OR, US

International Classification:

H01L 29/78
H01L 29/423
H01L 27/11
H01L 29/06
H01L 29/78
H01L 29/66

Abstract:

Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.

US Patent:

20160203999, Jul 14, 2016

Filed:

Sep 25, 2013

Appl. No.:

14/914627

Inventors:

- Santa Clara CA, US
NADIA RAHHAL-ORABI - LAKE OSWEGO OR, US
LEONARD P GULER - HILLSBORO OR, US
MICHAEL HARPER - HILLSBORO OR, US
RALPH THOMAS TROEGER - PORTLAND OR, US

International Classification:

H01L 21/311
H01L 21/02
H01L 21/8234
H01L 29/06
H01L 27/088
H01L 21/033
H01L 21/3105
H01L 29/40

Abstract:

Techniques and structures for protecting etched features during etch mask removal. In embodiments, a mask is patterned and a substrate layer etched to transfer the pattern. Subsequent to etching the substrate layer, features patterned into the substrate are covered with a sacrificial material backfilling the etch mask. At least a top portion of the mask is removed with the substrate features protected by the sacrificial material. The sacrificial material and any remaining portion of the mask are then removed. In further embodiments, a gate contact opening etched into a substrate layer is protected with a sacrificial material having the same composition as a first material layer of a multi-layered etch mask. A second material layer of the etch mask having a similar composition as the substrate layer is removed before subsequently removing the sacrificial material concurrently with the first mask material layer.

US Patent:

20160204193, Jul 14, 2016

Filed:

Jun 26, 2013

Appl. No.:

14/778063

Inventors:

Michael L. HATTENDORF - Portland OR, US
Pragyansri PATHI - Portland OR, US
Michael K. HARPER - Hillsboro OR, US

International Classification:

H01L 29/06
H01L 27/11
H01L 29/423
H01L 29/66
H01L 29/78

Abstract:

Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.