Michael Vance Harper

Address:

5873 NE Kettering St, Hillsboro, OR 97124

VIN:

5GZCZ53487S859686

Make:

SATURN

Model:

VUE

Year:

2007

US Patent:

7977248, Jul 12, 2011

Filed:

Dec 31, 2007

Appl. No.:

12/006204

Inventors:

Elliot Tan - Portland OR, US
Michael K. Harper - Hillsboro OR, US
James Jeong - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438717, 438585, 438587, 438399, 438696, 430313, 430311

Abstract:

In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.

US Patent:

8193641, Jun 5, 2012

Filed:

May 9, 2006

Appl. No.:

11/431388

Inventors:

Willy Rachmady - Beaverton OR, US
Brian McIntyre - Portland OR, US
Michael K. Harper - Hillsboro OR, US
Subhash M. Joshi - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257758, 257E2706, 257E2916

Abstract:

A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

US Patent:

8314034, Nov 20, 2012

Filed:

Dec 23, 2010

Appl. No.:

12/978160

Inventors:

Elliot N. Tan - Portland OR, US
Michael K. Harper - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438717, 438734, 438736, 438738, 257E21017, 257E2102

Abstract:

Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.

US Patent:

8377771, Feb 19, 2013

Filed:

May 23, 2012

Appl. No.:

13/479078

Inventors:

Willy Rachmady - Beaverton OR, US
Brian McIntrye - Portland OR, US
Michael K. Harper - Hillsboro OR, US
Subhash M. Joshi - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8238

US Classification:

438216, 257E21202

Abstract:

A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

US Patent:

8441074, May 14, 2013

Filed:

Jul 15, 2010

Appl. No.:

12/837321

Inventors:

Willy Rachmady - Beaverton OR, US
Justin S. Sandford - Tigard OR, US
Michael K. Harper - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/66

US Classification:

257365, 257369, 257E27062, 257E29264

Abstract:

A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

US Patent:

8629039, Jan 14, 2014

Filed:

May 2, 2013

Appl. No.:

13/875412

Inventors:

Willy Rachmady - Beaverton OR, US
Justin S. Sandford - Tigard OR, US
Michael K. Harper - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/76

US Classification:

438424, 257365, 257369, 257E27062, 257E29264

Abstract:

A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

US Patent:

20090321834, Dec 31, 2009

Filed:

Jun 30, 2008

Appl. No.:

12/215778

Inventors:

Willy Rachmady - Beaverton OR, US
Justin S. Sandford - Tigard OR, US
Michael K. Harper - Hillsboro OR, US

International Classification:

H01L 21/762
H01L 27/088

US Classification:

257365, 438424, 257E21546, 257E29264

Abstract:

A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

US Patent:

20210305430, Sep 30, 2021

Filed:

Mar 27, 2020

Appl. No.:

16/833208

Inventors:

- Santa Clara CA, US
Stephen SNYDER - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
William HSU - Hillsboro OR, US
Urusa ALAAN - Hillsboro OR, US
Tahir GHANI - Portland OR, US
Michael K. HARPER - Hillsboro OR, US
Vivek THIRTHA - Portland OR, US
Shu ZHOU - Portland OR, US
Nitesh KUMAR - Beaverton OR, US

International Classification:

H01L 29/78
H01L 29/423
H01L 29/06
H01L 29/165
H01L 29/10
H01L 29/08
H01L 21/02

Abstract:

Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.