Michael J Keith

US Patent:

53613708, Nov 1, 1994

Filed:

Oct 24, 1991

Appl. No.:

7/782332

Inventors:

David L. Sprague - Trenton NJ
Kevin Harney - Brooklyn NY
Michael Keith - Holland PA
Allen H. Simon - Belle Meade NJ
Michael Papadopoulos - Burlinton MA
Walter P. Hays - Brookline MA
George F. Salem - Cambridge MA
Shih-Wei Shiue - Lexington MA
Vitaly H. Shilman - Brookline MA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1516
G06F 1566
G06F 1580

US Classification:

395800

Abstract:

A single-instruction multiple-data video signal processor employs a dual-ported local memory architecture in each local memory including a dedicated port for transfers between the local memory and a global memory. A block transfer controller, in combination with the dedicated port, permit each access to the global memory by a datapath processor to be overlapped with its instruction processing, thus usually avoiding stalling of the video signal processor.

US Patent:

55176658, May 14, 1996

Filed:

Apr 21, 1994

Appl. No.:

8/230915

Inventors:

David L. Sprague - Trenton NJ
Kevin Harney - Brooklyn NY
Michael Keith - Holland PA
Allen H. Simon - Belle Meade NJ
Gregory M. Papadopoulos - Burlinton MA
Walter P. Hays - Brookline MA
George F. Salem - Cambridge MA
Shih-Wei Shiue - Lexington MA
Anthony P. Bertapelli - Ayer MA
Vitaly H. Shilman - Brookline MA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1516
G06F 1300

US Classification:

395800

Abstract:

A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

US Patent:

54505445, Sep 12, 1995

Filed:

Dec 16, 1994

Appl. No.:

8/357544

Inventors:

Doug Dixon - Hopewell NJ
Judith Goldstein - Browns Mills NJ
Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 100

US Classification:

395164

Abstract:

A method and apparatus for storing a sequence of compressed frames of digital motion video information in a circular buffer is disclosed. In a preferred embodiment, compressed digital motion video information is written from a storage device to the circular buffer. A host pointer is set equal to the location corresponding to the end of the last frame of motion video information written to the circular buffer, and the positions of a microcode pointer and the host pointer are compared. Based on these positions, determinations are made regarding (i) whether a compressed frame of digital motion video information is present in the circular buffer and ready for decompression and (ii) whether a portion of the circular buffer can be re-written with compressed digital motion video data based on the positions of the microcode and host pointers.

US Patent:

53849043, Jan 24, 1995

Filed:

Dec 8, 1992

Appl. No.:

7/987725

Inventors:

David L. Sprague - Trenton NJ
Michael Keith - Holland PA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1560

US Classification:

395139

Abstract:

A method for performing scaling of a video image uses a noninteger scale factor. The scaling using a series of images scaled according to integer powers of two. An integer scale factor is applied to the image to be scaled in order to provide a series of scaled images. A determination is made which scaled image is the closest image to the one corresponding to the fractional scale factor. The scaled image selected in this manner is then operated upon using an interpolation to obtain the value corresponding to the fractional scale factor. Alternatively, the two scaled images which are closest to the image corresponding to the fractional scale factor may be selected and an interpolation operation or an averaging operation of the two scaled images may be performed to obtain the factional scale image. The scaled images may be predetermined during off-line operations so that a plurality of image selections may be performed upon the same set of predetermined scaled images.

US Patent:

55308848, Jun 25, 1996

Filed:

Apr 21, 1994

Appl. No.:

8/230900

Inventors:

David L. Sprague - Trenton NJ
Kevin Harney - Brooklyn NY
Michael Keith - Holland PA
Allen H. Simon - Belle Meade NJ
Gregory M. Papadopoulos - Burlington MA
Walter P. Hays - Brookline MA
George F. Salem - Cambridge MA
Shih-Wei Shiue - Lexington MA
Anthony P. Bertapelli - Ayer MA
Vitaly H. Shilman - Brookline MA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300
G06F 1516

US Classification:

395800

Abstract:

A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.

US Patent:

54308542, Jul 4, 1995

Filed:

Oct 27, 1993

Appl. No.:

8/144219

Inventors:

David L. Sprague - Trenton NJ
Kevin Harney - Brooklyn NY
Michael Keith - Holland PA
Allen H. Simon - Belle Meade NJ
Michael Papadopoulos - Burlinton MA
Walter P. Hays - Brookline MA
George F. Salem - Cambridge MA
Shih-Wei Shiue - Lexington MA
Anthony P. Bertapelli - Ayer MA
Vitaly H. Shilman - Brookline MA

International Classification:

G06F 1580

US Classification:

395375

Abstract:

A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.

US Patent:

52628558, Nov 16, 1993

Filed:

Mar 25, 1992

Appl. No.:

7/856515

Inventors:

Adnan M. Alattar - Plainsboro NJ
Michael Keith - Holland PA
Stuart J. Golin - East Windsor NJ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 712

US Classification:

358133

Abstract:

A method and apparatus for encoding a sequence of digital motion video images at more than one resolution. In a first embodiment, it is determined whether an image selected from the sequence is part of either a dissolve, a fade, a fast motion region or a complex motion region. If the selected image is part of either a dissolve, a fade, a fast motion region or a complex motion region, then the selected image is encoded at a reduced resolution level. In a further embodiment, a selected image is provided for encoding. A determination is then made whether a parameter derived from an estimate of the available decoding time is above a predetermined threshold. If the parameter is above the predetermined threshold, then the selected image is encoded at a reduced resolution. In a still further embodiment, a selected image from a sub-sequence of images is provided for encoding. A determination is then made whether the quantization step size associated with the image is greater than a predetermined threshold.

US Patent:

55487939, Aug 20, 1996

Filed:

Apr 21, 1994

Appl. No.:

8/230899

Inventors:

David L. Sprague - Trenton NJ
Kevin Harney - Brooklyn NY
Michael Keith - Holland PA
Allen H. Simon - Belle Meade NJ
Gregory M. Papadopoulos - Burlinton MA
Walter P. Hays - Brookline MA
George F. Salem - Cambridge MA
Shih-Wei Shiue - Lexington MA
Anthony P. Bertapelli - Ayer MA
Vitaly H. Shilman - Brookline MA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 1516

US Classification:

395860

Abstract:

A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.