Michael Kilgore

US Patent:

7144822, Dec 5, 2006

Filed:

Feb 6, 2002

Appl. No.:

10/072357

Inventors:

Michael D. Kilgore - Santa Clara CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/469
H01L 21/31
H01L 21/4763

US Classification:

438758, 438624, 438778, 438788, 438792

Abstract:

A method for plasma processing of semiconductor wafers is provided that reduces plasma-induced damage to the gate dielectric while limiting damage to the wafer from particulates that flake off of the interior surfaces of the reaction chamber. Plasma conditions are maintained in the reaction chamber while the wafer is transferred into the chamber and the plasma process is performed. After the plasma process, while still maintaining plasma conditions, the wafer is cooled to a removal temperature and removed from the reaction chamber.

US Patent:

7558045, Jul 7, 2009

Filed:

Mar 20, 2008

Appl. No.:

12/052395

Inventors:

Jaime Onate - Fremont CA, US
Michael Kilgore - Sunnyvale CA, US
Jimmy Lam - Fremont CA, US
Timothy W. Kueper - Santa Clara CA, US
Dan Ye - Sunnyvale CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/683

US Classification:

361234

Abstract:

A semiconductor workpiece processing system for treating a workpiece, such as a semiconductor wafer, is provided. A related operating control method is also provided. The system includes an electrostatic chuck configured to receive a workpiece, and a clamping voltage power supply coupled to the electrostatic chuck. The electrostatic chuck has a clamping electrode assembly, and the clamping voltage power supply is coupled to the clamping electrode assembly. The clamping voltage power supply includes a direct current (DC) voltage generator configured to generate a DC clamping voltage for the clamping electrode assembly, an alternating current (AC) voltage generator configured to generate an AC excitation signal for the clamping electrode assembly, and a processing architecture coupled to the clamping electrode assembly. The processing architecture is configured to analyze attributes of a workpiece presence signal obtained in response to the AC excitation signal, and, based on the attributes, verify proper/improper positioning of the workpiece relative to the electrostatic chuck.

US Patent:

20100008016, Jan 14, 2010

Filed:

Jul 7, 2009

Appl. No.:

12/498976

Inventors:

Jaime Onate - Fremont CA, US
Michael Kilgore - Sunnyvale CA, US
Jimmy Lam - Fremont CA, US
Timothy W. Kueper - Santa Clara CA, US
Dan Ye - Sunnyvale CA, US

Assignee:

NOVELLUS SYSTEMS, INC. - San Jose CA

International Classification:

H01L 21/683

US Classification:

361234

Abstract:

A semiconductor workpiece processing system for treating a workpiece, such as a semiconductor wafer, is provided. A related operating control method is also provided. The system includes an electrostatic chuck configured to receive a workpiece, and a clamping voltage power supply coupled to the electrostatic chuck. The electrostatic chuck has a clamping electrode assembly, and the clamping voltage power supply is coupled to the clamping electrode assembly. The clamping voltage power supply includes a direct current (DC) voltage generator configured to generate a DC clamping voltage for the clamping electrode assembly, an alternating current (AC) voltage generator configured to generate an AC excitation signal for the clamping electrode assembly, and a processing architecture coupled to the clamping electrode assembly. The processing architecture is configured to analyze attributes of a workpiece presence signal obtained in response to the AC excitation signal, and, based on the attributes, verify proper/improper positioning of the workpiece relative to the electrostatic chuck.

US Patent:

62004123, Mar 13, 2001

Filed:

Feb 16, 1996

Appl. No.:

8/602641

Inventors:

Michael D. Kilgore - Santa Clara CA
Wilbert G. M. van den Hoek - Cupertino CA
Christopher J. Rau - Milpitas CA
Bart J. van Schravendijk - Sunnyvale CA
Jeffrey A. Tobin - Mountain View CA
Thomas W. Mountsier - San Jose CA
James C. Oswalt - Pleasanton CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

B65C 326
C23C 1600
H01L 2100

US Classification:

156345

Abstract:

A plasma-enhanced chemical vapor deposition system includes a number of process gas injection tubes and at least one dedicated clean gas injection tube. A plasma is used to periodically clean the interior surfaces of the deposition chamber. The cleaning is made more rapid and effective by introducing the clean gas through the dedicated clean gas injection tube. In this manner the clean gas can be introduced at a relatively high flow rate without detracting from the cleaning of the interior surfaces of the process gas injection tubes. As a separate aspect of this invention, a high-frequency signal is applied to both terminals of the coil during the cleaning process. This produces a plasma, mainly by capacitive coupling, which has a shape and uniformity that are well-suited to cleaning the surfaces of the deposition chamber.