Michael R Lambert

US Patent:

20040015338, Jan 22, 2004

Filed:

Jul 19, 2002

Appl. No.:

10/199635

Inventors:

William Lawrence - Windsor CO, US
Francisco Ostojic - Fort Collins CO, US
Michael Lambert - Fort Collins CO, US
Robert Martin - Timnath CO, US
Edward Weber - Ft. Collins CO, US

International Classification:

G06G007/62

US Classification:

703/013000, 324/500000

Abstract:

The present invention is directed to a method and apparatus for simulating digital electronic systems. The signal integrity of a digital electronic system is assessed by analyzing traces (e.g. wires between components) for cross coupling. Problem areas are identified by monitoring storage components or output ports of the electronic system. Wires (traces), which carry signal transitions to the storage component or output ports are analyzed and quantified based on timing windows associated with the wires (traces). The clock transitions into a storage device are analyzed and vulnerability windows are identified for the storage device. The vulnerability windows are time periods when cross coupling may occur on a storage device. If a timing window overlaps a vulnerability window the timing window is considered a critical timing window. Devices driving the transition on wires with critical timing windows are then analyzed. Adjustments are made to the parameters of the driving devices to create a worse case scenario. The worse case scenario is simulated and analyzed for cross-coupling.

US Patent:

20040015737, Jan 22, 2004

Filed:

Jul 19, 2002

Appl. No.:

10/199138

Inventors:

Robert Martin - Timnath CO, US
William Lawrence - Windsor CO, US
Francisco Ostojic - Fort Collins CO, US
Mark Hammer - Loveland CO, US
Michael Lambert - Fort Collins CO, US
Edward Weber - Ft. Collins CO, US

International Classification:

H04B001/74

US Classification:

714/026000

Abstract:

A method of characterizing and simulating electronic systems for signal integrity is presented. Each device in the electronic system is associated with at least one vulnerability table and at least one vulnerability window. The vulnerability table is a three dimensional table that characterizes the operation of the device and includes line length on one axis, coupling efficiency on another axis and drivers size of a gate, on the third axis. In addition a number of vulnerability windows are presented. The vulnerability window is a time period when a storage device may store the wrong data because of signal integrity issues in the electronic system. A vulnerability window is developed for each input to a storage device in the system. In addition a vulnerability window is developed based on a number of failure mechanisms used to characterize the system. Lastly, a mapped vulnerability window is presented for devices such as logical gates, which provide input to the storage device. The mapped vulnerability windows are a function of the vulnerability windows for the storage device and the time delay for a signal communicated from a gate under study to the storage device.

US Patent:

20050210349, Sep 22, 2005

Filed:

Mar 22, 2004

Appl. No.:

10/806485

Inventors:

Michael Lambert - Fort Collins CO, US
John Rohrbaugh - Fort Collins CO, US

International Classification:

G01R031/28

US Classification:

714726000

Abstract:

Tools, systems and/or methods for use in a test process of a circuit device. Such tools, systems and/or methods may provide for identifying respective parent and branch portions of a scan chain of a circuit device, the scan chain having at least one scan input and one or more scan outputs and a plurality of scan cells; and creating a model of the scan chain, including creating a dummy cell chain which includes a branch portion of the scan chain and has one or more dummy cells disposed therein connected between the branch portion and the scan input.