Michael Scott Lyons

US Patent:

6388528, May 14, 2002

Filed:

Sep 24, 2001

Appl. No.:

09/961599

Inventors:

Kenneth V. Buer - Gilbert AZ
Christopher D. Grondahl - Chandler AZ
Michael R. Lyons - Gilbert AZ

Assignee:

U.S. Monolithics, L.L.C. - Chandler AZ

International Classification:

H03F 368

US Classification:

330295, 330307

Abstract:

A MMIC power amplifier having a smaller die size and higher power output are realized with the improved amplifier and transistor geometry herein provided. In particular, transistors, such as FETs (field effect transistors) are displaced from a conventional FET geometry with alternating FETs being rotated in opposite directions. The inputs (gate pads) and outputs (drain pads) of two adjacent FETs may be âshared. â In a shared input configuration, a compensation network may be coupled to the input. The improved FET configuration reduces the number of splitting and combining networks by up to 50% over the prior art and the die area for a typical 4 watt power amplifier is reduced by 48-72% over the prior art. The improved amplifier configuration provides a multi-sectional configuration wherein one section may be the mirrored image of another. In a two section amplifier, the amplifier appears to be âfolded. â.

US Patent:

6542035, Apr 1, 2003

Filed:

Dec 28, 2000

Appl. No.:

09/750927

Inventors:

Dean L. Cook - Mesa AZ
Michael R. Lyons - Tempe AZ
John Martin Peitz - Mesa AZ
Edwin Jack Stanfield - Queencreek AZ

Assignee:

U.S. Monolithics, L.L.C. - Chandler AZ

International Classification:

H03F 360

US Classification:

330286, 330 53, 330 66, 330124 R, 330307

Abstract:

A modular high power solid state amplifier and method of assembly, manufacture and use are herein disclosed. The high power amplifier includes a number of amplifiers, a DC board having flexible interconnects, a RF cover including an interlocking RF input, a RF board, a chassis, and a top cover; thereby providing an encased stand-alone solid state amplifier. The solid state components, angled designs, and piggyback topology of the invention provide a compact, efficient, integrated high power amplifier device.

US Patent:

7489022, Feb 10, 2009

Filed:

Aug 2, 2005

Appl. No.:

11/161420

Inventors:

Richard S Torkington - Mesa AZ, US
Michael R Lyons - Gilbert AZ, US
Kenneth V Buer - Gilbert AZ, US

Assignee:

Viasat, Inc. - Carlsbad CA

International Classification:

H01L 23/495

US Classification:

257666, 438106

Abstract:

An over-molded leadframe (e. g. , a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the QFN package are disclosed. The QFN package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip.

US Patent:

7583150, Sep 1, 2009

Filed:

Mar 20, 2007

Appl. No.:

11/688729

Inventors:

Kenneth V Buer - Gilbert AZ, US
Michael Lyons - Gilbert AZ, US
Scarlet Daoud - Mesa AZ, US

Assignee:

ViaSat, Inc. - Carlsbad CA

International Classification:

H03F 3/68

US Classification:

330310, 330133, 330150

Abstract:

A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

US Patent:

7948324, May 24, 2011

Filed:

Aug 10, 2009

Appl. No.:

12/538437

Inventors:

Kenneth V. Buer - Gilbert AZ, US
Michael Lyons - Gilbert AZ, US
Scarlet Daoud - Mesa AZ, US

Assignee:

ViaSat, Inc. - Carlsbad CA

International Classification:

H03F 3/68

US Classification:

330310, 330133, 330150

Abstract:

A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.

US Patent:

8035203, Oct 11, 2011

Filed:

Feb 9, 2009

Appl. No.:

12/367932

Inventors:

Richard S. Torkington - Mesa AZ, US
Michael R. Lyons - Gilbert AZ, US
Kenneth V. Buer - Gilbert AZ, US

Assignee:

ViaSat, Inc. - Carlsbad CA

International Classification:

H01L 23/495
H01L 21/66

US Classification:

257666, 438 15

Abstract:

An over-molded leadframe (e. g. , a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip.

US Patent:

8072065, Dec 6, 2011

Filed:

Feb 14, 2008

Appl. No.:

12/031236

Inventors:

Noel A. Lopez - Phoenix AZ, US
Michael R. Lyons - Gilbert AZ, US
Dave Laidig - Mesa AZ, US
Kenneth V. Buer - Gilbert AZ, US

Assignee:

ViaSat, Inc. - Carlsbad CA

International Classification:

H01L 23/34

US Classification:

257728, 257705, 257E2301

Abstract:

A millimeter wave system or package may include at least one printed wiring board (PWB), at least one integrated waveguide interface, and at least one monolithic microwave integrated circuit (MMIC). The package may be assembled in panel form incorporating parallel manufacturing techniques.

US Patent:

8384498, Feb 26, 2013

Filed:

Nov 6, 2009

Appl. No.:

12/613724

Inventors:

Christopher D. Grondahl - Gilbert AZ, US
Michael R. Lyons - Gilbert AZ, US
Dean Lawrence Cook - Mesa AZ, US

Assignee:

ViaSat, Inc. - Carlsbad CA

International Classification:

H01P 1/203
H01P 7/08

US Classification:

333204, 333219

Abstract:

In an exemplary embodiment, a spurline filter comprises a capacitive element connected to a spur and either a through-line of the spurline filter or ground. In another embodiment, multiple capacitive elements are connected to the spur. In an exemplary embodiment, the capacitively loaded spurline filter provides a band rejection frequency response similar to the band rejection frequency response of a similar spurline filter that does not comprise at least one capacitive element but the capacitively loaded spurline filter has half the layout area or less. In an exemplary embodiment, the spurline filter comprises capacitive elements, where the capacitive elements are configured to reduce the resonant frequency of the filter.