Michael N May

US Patent:

6362605, Mar 26, 2002

Filed:

Aug 24, 2000

Appl. No.:

09/645722

Inventors:

Michael R May - Austin TX

Assignee:

Sigmatel, Inc. - Austin TX

International Classification:

G05F 156

US Classification:

323265, 330255

Abstract:

A method and apparatus for efficiently powering an integrated circuit include processing that begins by generating a representation of a battery voltage. The processing then continues by producing a regulated bias current based on the representation of the battery voltage. The processing continues by providing the regulated bias current to an external crystal, which, in turn, generates an oscillation in response to the bias current. The processing then continues by generating a clock signal from the oscillation produced by the external crystal. The clock signal is then provided to a DC-to-DC converter that converts the battery voltage into a regulated output voltage.

US Patent:

D458873, Jun 18, 2002

Filed:

Jul 30, 2001

Appl. No.:

29/145683

Inventors:

Young Choi - Redondo Beach CA
Michael P. May - Rolling Hills Estates CA

Assignee:

Honda Giken Kogyo Kabushiki Kaisha - Tokyo

International Classification:

1208

US Classification:

D12 92

US Patent:

6567027, May 20, 2003

Filed:

Feb 8, 2001

Appl. No.:

09/779810

Inventors:

Michael R. May - Austin TX

Assignee:

Sigmatel, Inc. - Austin TX

International Classification:

H03M 700

US Classification:

341155, 341143

Abstract:

A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.

US Patent:

6522275, Feb 18, 2003

Filed:

Feb 8, 2001

Appl. No.:

09/779158

Inventors:

Michael R. May - Austin TX

Assignee:

Sigmatel, Inc. - Austin TX

International Classification:

H03M 300

US Classification:

341143, 341 61

Abstract:

A method and apparatus for sample rate conversion in an analog to digital converter includes processing that begins by converting an analog input signal into a stream of digital data. The processing continues by determining an up sampling value and a down sampling value based on a sample rate conversion value. The processing continues by computing a moving sum of data of the stream of data based on the up sampling value, the clock rate of the stream of data, and a predetermined filter function. The processing continues by producing a digital output value from the moving sum based on the down sampling value, wherein the digital output value is at a desired output rate.

US Patent:

6617032, Sep 9, 2003

Filed:

Aug 31, 2001

Appl. No.:

09/945274

Inventors:

Stephen Rickner - Irvine CA
Joseph Jibrail - Mission Viejo CA
Jose Camba - West Covina CA
Carlos Velasco, Jr. - Corona CA
Calvin Peeler - Canton MI
Michael May - Clawson MI

Assignee:

BASF Corporation - Mt. Olive NJ

International Classification:

B32B 2740

US Classification:

4284233, 428213, 4282974

Abstract:

A composite structure including a polyurea show surface, or top layer, and a polyurethane backing layer is disclosed. Preferably, the show surface of the composite structure is substantially free of volatile organic compounds and is aliphatic such that it is ultraviolet light stable. Specifically, the show surface is the reaction product of an aliphatic polyisocyanate or aliphatic polyisocyanate blend, and of a resin component which is a polyamine. The resin component reacts with the aliphatic polyisocyanate to form a polyurea. The show surface has a Shore D hardness of 70. Like the show surface, the polyurethane backing layer of the composite structure is substantially free of volatile organic compounds. This backing layer is the reaction product of a second polyisocyanate component, such as polymeric diphenylmethane diisocyanate, and of a second-layer resin component, which comprises a polyol having a functionality of at least three. The complete composite structure has a flexural modulus of at least 200,000 lb/in.

US Patent:

6633187, Oct 14, 2003

Filed:

Nov 20, 2000

Appl. No.:

09/716731

Inventors:

Michael R. May - Austin TX
Marcus W. May - Austin TX

Assignee:

Sigmatel, Inc. - Austin TX

International Classification:

H03K 302

US Classification:

327198, 327544

Abstract:

A method and apparatus for enabling a stand-alone integrated circuit (IC) includes processing that begins by establishing an idle state that holds at least a portion of the stand-alone integrated circuit in a reset condition when a power source is operably coupled to the stand-alone integrated circuit. A stand-alone integrated circuit includes generally an on-chip power converter, a reset circuit and some functional circuitry, which may be a microprocessor, digital signal processor digital circuitry, state machine, logic circuitry, analog circuitry, and/or any type of components and/or circuits that perform a desired electrical function. When a power enable signal is received, the on-chip power converter is enabled to generate at least 1 supply from the power source. The processing continues by enabling functionality of the stand-alone integrated circuit when the at least one supply has substantially reached a steady state condition.

US Patent:

6753705, Jun 22, 2004

Filed:

Jul 27, 2000

Appl. No.:

09/626574

Inventors:

Michael R. May - Austin TX

Assignee:

Sigmatel, Inc. - Austin TX

International Classification:

H03K 522

US Classification:

327 24, 327 26, 327 87, 327552

Abstract:

An edge sensitive detection circuit includes a filter module and a soft latch module. The filter module is operably coupled to receive an input logic signal that corresponds to the triggering of an event and produces a pulse signal in response to an edge of the input logic signal. The filter may include a capacitor operably coupled to a controlled impedance, an inverter and a driver transistor, wherein the capacitor senses an edge of the input logic signal and, in combination with the controlled impedance, produces the pulse signal. The soft latch module is operably coupled to receive the pulse signal and to latch a logic value in accordance with the pulse signal.

US Patent:

6841111, Jan 11, 2005

Filed:

Aug 31, 2001

Appl. No.:

09/944561

Inventors:

Stephen Rickner - Irvine CA, US
Joseph Jibrail - Mission Viejo CA, US
Jose Camba - West Covina CA, US
Carlos Velasco, Jr. - Corona CA, US
Calvin Peeler - Canton MI, US
Michael May - Clawson MI, US

Assignee:

BASF Corporation - Mt. Olive NJ

International Classification:

B29C 4516

US Classification:

264250, 264251, 264255, 4284233

Abstract:

A method of making a polyurea—polyurethane composite structure that is substantially free from emission of volatile organic compounds is disclosed. The composite structure produced according to the method of the subject invention has a flexural modulus of at least 200,000 lb/in. The composite structure includes first and second layers. A mold substrate is provided and a first-layer polyisocyanate component and a first-layer resin component are reacted and sprayed onto the mold substrate to form the first-layer. The first-layer polyisocyanate component includes an aliphatic polyisocyanate, and the first-layer resin component includes a polyamine thereby forming a polyurea show surface having a Shore D hardness of at least 65. After application of the first-layer, a second-layer polyisocyanate component and a second-layer resin component are reacted and sprayed behind the first-layer to form the second-layer of the composite structure. The second layer resin component more specifically includes a polyol having a theoretical functionality of at least three.