Michael J Mcgowan

US Patent:

6364932, Apr 2, 2002

Filed:

May 2, 2000

Appl. No.:

09/561980

Inventors:

Wenchang Ji - Doylestown PA
Arthur I. Shirley - Piscataway NJ
Michael Joseph McGowan - Valley Cottage NY
Daniel Arthur Morgan - Westfield NJ

Assignee:

The BOC Group, Inc. - Murray Hill NJ

International Classification:

B01D 4624

US Classification:

95 12, 95 45, 95 96, 95279, 95283, 427345, 427377

Abstract:

The present invention provides an improved cold gas-dynamic spraying process utilizing a carrier gas and small-diameter particulates whereby the particulate-laden carrier gas is directed to a ceramic filter unit where the particulates are separated out and the particulate-free carrier gas is analyzed and returned to the spraying process or to other gas purification systems.

US Patent:

6825716, Nov 30, 2004

Filed:

Apr 30, 2002

Appl. No.:

10/135645

Inventors:

Michael J. McGowan - Mesa AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03F 102

US Classification:

330 9, 330 69, 327124

Abstract:

A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.

US Patent:

7075473, Jul 11, 2006

Filed:

Apr 30, 2002

Appl. No.:

10/135789

Inventors:

Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M 1/36

US Classification:

341159, 341120

Abstract:

A system and apparatus for reducing the effects of circuit mismatch in analog-to-digital converters is disclosed. In one form, an analog-to-digital converter (ADC) includes a switching network operable to couple an analog input received by a sample and hold module to a folding amplifier operable to process the analog input. The ADC further includes an averaging resistive network coupled to the folding amplifier and operable to provide an output representative of a portion of the analog input received by the folding amplifier to produce a digital representation of the analog input.

US Patent:

7305642, Dec 4, 2007

Filed:

Apr 5, 2005

Appl. No.:

11/100039

Inventors:

James F. McClellan - Gilbert AZ, US
Patrick G. Drennan - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US
David R. LoCascio - Chandler AZ, US
Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50
G06F 19/00

US Classification:

716 10, 716 5, 700 97, 700121

Abstract:

The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

US Patent:

7305643, Dec 4, 2007

Filed:

May 12, 2005

Appl. No.:

11/128659

Inventors:

James F. McClellan - Gilbert AZ, US
Patrick G. Drennan - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US
David R. LoCascio - Chandler AZ, US
Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 10, 716 9, 716 11

Abstract:

A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

US Patent:

8353211, Jan 15, 2013

Filed:

Apr 27, 2011

Appl. No.:

13/095592

Inventors:

Yevgeniy Vinshtok - Allentown PA, US
Michael J. Mcgowan - Downingtown PA, US
Peter Breh - West Chester PA, US

Assignee:

IFM Electronic GmbH - Tettnang

International Classification:

G01D 11/24
G01L 19/14

US Classification:

73431

Abstract:

A sensor has a corpus comprising an insert opening through which a sensor element can be inserted in the corpus, and a cable opening for passing through a supply and/or signal line of the sensor element and a cover closing the insert opening. The cover comprises an interlock opening aligned with the cable opening. The supply and/or signal line comprises a bushing element which penetrates the cable opening of the corpus and the interlock opening of the cover.

US Patent:

8558727, Oct 15, 2013

Filed:

May 18, 2011

Appl. No.:

13/110686

Inventors:

Michael Joseph McGowan - Mesa AZ, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03M 1/00

US Classification:

341136, 341144

Abstract:

Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively, a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, and a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together. In another aspect, switching glitches are scaled based on a size difference between the switching transistors and the compensation transistors.

US Patent:

20090095074, Apr 16, 2009

Filed:

Oct 12, 2007

Appl. No.:

11/871969

Inventors:

Yevgeniy Vinshtok - Allentown PA, US
Michael J. McGowan - Downingtown PA, US
Peter Breh - West Chester PA, US
Ralf Siegler - Schlier, DE
Michael Becker - Tettnang, DE

International Classification:

G01D 11/24

US Classification:

73431

Abstract:

A sensor has a corpus () comprising an insert opening () through which a sensor element () can be inserted in the corpus (), and a cable opening for passing through a supply and/or signal line () of the sensor element (), and a cover () closing the insert opening (), The cover () comprises an interlock opening () aligned with the cable opening. The supply and/or signal line () comprises a bushing element () which penetrates the cable opening of the corpus () and the interlock opening () of the cover ().