Michael E Mcgowan

US Patent:

6825716, Nov 30, 2004

Filed:

Apr 30, 2002

Appl. No.:

10/135645

Inventors:

Michael J. McGowan - Mesa AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03F 102

US Classification:

330 9, 330 69, 327124

Abstract:

A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.

US Patent:

7075473, Jul 11, 2006

Filed:

Apr 30, 2002

Appl. No.:

10/135789

Inventors:

Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M 1/36

US Classification:

341159, 341120

Abstract:

A system and apparatus for reducing the effects of circuit mismatch in analog-to-digital converters is disclosed. In one form, an analog-to-digital converter (ADC) includes a switching network operable to couple an analog input received by a sample and hold module to a folding amplifier operable to process the analog input. The ADC further includes an averaging resistive network coupled to the folding amplifier and operable to provide an output representative of a portion of the analog input received by the folding amplifier to produce a digital representation of the analog input.

US Patent:

7305642, Dec 4, 2007

Filed:

Apr 5, 2005

Appl. No.:

11/100039

Inventors:

James F. McClellan - Gilbert AZ, US
Patrick G. Drennan - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US
David R. LoCascio - Chandler AZ, US
Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50
G06F 19/00

US Classification:

716 10, 716 5, 700 97, 700121

Abstract:

The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

US Patent:

7305643, Dec 4, 2007

Filed:

May 12, 2005

Appl. No.:

11/128659

Inventors:

James F. McClellan - Gilbert AZ, US
Patrick G. Drennan - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US
David R. LoCascio - Chandler AZ, US
Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 10, 716 9, 716 11

Abstract:

A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

US Patent:

8558727, Oct 15, 2013

Filed:

May 18, 2011

Appl. No.:

13/110686

Inventors:

Michael Joseph McGowan - Mesa AZ, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03M 1/00

US Classification:

341136, 341144

Abstract:

Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively, a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, and a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together. In another aspect, switching glitches are scaled based on a size difference between the switching transistors and the compensation transistors.

US Patent:

59208104, Jul 6, 1999

Filed:

May 5, 1997

Appl. No.:

8/851236

Inventors:

Jesus Lucidio Finol - Gilbert AZ
Michael J. McGowan - Mesa AZ
Philippe Gorisse - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 126

US Classification:

455313

Abstract:

A multiplier (10) includes a transconductor (14) and a multiplier core (34). The transconductor (14) converts an RF voltage signal to an RF current signal. The RF current signal modulates the quiescent currents flowing in current conducting elements (23, 24), thereby generating a modulated current signal. The modulated current signal is transmitted to the multiplier core (34), where it is combined with an LO signal to generate an output signal. The transconductor (14) and the multiplier core (34) have their current conduction paths separated from each other by the current conducting elements (23, 24).

US Patent:

20230068051, Mar 2, 2023

Filed:

Aug 27, 2021

Appl. No.:

17/459063

Inventors:

Michael McGowan - San Jose CA, US

International Classification:

A47K 10/12
A47K 10/02

Abstract:

A towel having a plurality of magnets and pockets is provided. In one embodiment, a towel includes magnets in rows, whereby a folding of the towel aligns some magnets with other magnets and thereby facilitates a hanging of the towel on other objects. The pockets are configured on the towel such that when the towel is folded the pockets are within the folds of the towel to ensure that objects placed in the pockets are secured within the folds of the towel. In certain embodiments, the towel can have two surfaces. One surface can be of a smooth material while the other surface can be of a rough material. In one embodiment, the invention is a foldable piece of material with magnets configured on the piece such that a folding of the piece allows the piece to be hung on an item via the interaction of the magnets.

US Patent:

20210154255, May 27, 2021

Filed:

Feb 8, 2021

Appl. No.:

17/170735

Inventors:

Michael McGowan - San Jose CA, US

International Classification:

A61K 36/185
A61K 31/352
A61F 6/00
A61K 9/00

Abstract:

There is a composition comprising an essential oil, namely a essential oil that is compatible with a prophylactic such as a condom. The essential oil comprises an active ingredient, tetrahydrocannabinol, which heightens the sensation and causes a euphoric feeling during intimate relations. There is a kit allowing for easy access to both the essential oil and condom that comprises two chambers, one chamber for storing the essential oil and the second chamber for storing the condom. The two chambers are easily separable by tearing along the perforated portion. There is a packet comprising two separable chambers for storing the composition comprising the essential oil and a prophylactic.