Michael P Mcgowan

US Patent:

6825716, Nov 30, 2004

Filed:

Apr 30, 2002

Appl. No.:

10/135645

Inventors:

Michael J. McGowan - Mesa AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03F 102

US Classification:

330 9, 330 69, 327124

Abstract:

A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.

US Patent:

7075473, Jul 11, 2006

Filed:

Apr 30, 2002

Appl. No.:

10/135789

Inventors:

Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M 1/36

US Classification:

341159, 341120

Abstract:

A system and apparatus for reducing the effects of circuit mismatch in analog-to-digital converters is disclosed. In one form, an analog-to-digital converter (ADC) includes a switching network operable to couple an analog input received by a sample and hold module to a folding amplifier operable to process the analog input. The ADC further includes an averaging resistive network coupled to the folding amplifier and operable to provide an output representative of a portion of the analog input received by the folding amplifier to produce a digital representation of the analog input.

US Patent:

7305642, Dec 4, 2007

Filed:

Apr 5, 2005

Appl. No.:

11/100039

Inventors:

James F. McClellan - Gilbert AZ, US
Patrick G. Drennan - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US
David R. LoCascio - Chandler AZ, US
Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50
G06F 19/00

US Classification:

716 10, 716 5, 700 97, 700121

Abstract:

The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

US Patent:

7305643, Dec 4, 2007

Filed:

May 12, 2005

Appl. No.:

11/128659

Inventors:

James F. McClellan - Gilbert AZ, US
Patrick G. Drennan - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US
David R. LoCascio - Chandler AZ, US
Michael J. McGowan - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 10, 716 9, 716 11

Abstract:

A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

US Patent:

7690711, Apr 6, 2010

Filed:

Sep 3, 2008

Appl. No.:

12/203225

Inventors:

Michael P. McGowan - Sterling Heights MI, US
Edward L. Schulte - White Lake MI, US
Derek L. Patterson - Shelby Township MI, US
Balakrishna Chinta - Troy MI, US

Assignee:

GM Global Technology Operations, Inc. - Detroit MI

International Classification:

B62D 33/03
B62D 33/033

US Classification:

296 571, 296 52, 296 59

Abstract:

An endgate assembly connectable to a vehicle body for opening and closing a vehicle bed formed by the body includes an endgate supportable by the vehicle body at a pivot connection and openable and closable by pivoting about the pivot connection. A keyed support member is securable to the vehicle body. A damper and a cable are connected to the endgate. Both the damper and the cable have ends that are configured to be retained by the keyed support member when the endgate is pivoted between the open and closed position. The cable and damper ends can be removed from the keyed support member without tools when the cable end is rotated relative to the keyed support member. A method of modifying the vehicle bed by detaching or reattaching the endgate assembly is also provided.

US Patent:

8558727, Oct 15, 2013

Filed:

May 18, 2011

Appl. No.:

13/110686

Inventors:

Michael Joseph McGowan - Mesa AZ, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03M 1/00

US Classification:

341136, 341144

Abstract:

Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively, a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, and a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together. In another aspect, switching glitches are scaled based on a size difference between the switching transistors and the compensation transistors.

US Patent:

20110256418, Oct 20, 2011

Filed:

Apr 19, 2010

Appl. No.:

12/762629

Inventors:

Michael P. McGowan - Sterling Heights MI, US
Scott S. Moore - Royal Oak MI, US
Nicholas M. Bosway - Clarkston MI, US

Assignee:

GM GLOBAL TECHNOLOGY OPERATIONS, INC. - DETROIT MI

International Classification:

B32B 15/01
B32B 3/10
C25D 13/00
B32B 3/00

US Classification:

428594, 428172, 428137, 204471

Abstract:

An assembly for limiting corrosion between a first member made of a first material and a second member made of a second material, different from the first material, includes a plurality of cylindrical dimples defined in the first member. The cylindrical dimples are formed as a one-piece structure with the first member. The cylindrical dimples and the second member interact to define a plurality of galvanic contact zones. An electrocoat covers substantially all of the first member and the second member, but does not cover the galvanic contact zones. Therefore, the galvanic contact zones are not in contact with the electrocoat and are sealed to prevent contact with an electrolyte. A method of assembling a first member to a second member, to limit corrosion therebetween, is also provided.

US Patent:

51592053, Oct 27, 1992

Filed:

Oct 24, 1990

Appl. No.:

7/603900

Inventors:

James L. Gorecki - Vail AZ
Michael J. McGowan - Tuscon AZ

Assignee:

Burr-Brown Corporation - Tucson AZ

International Classification:

H03K 5159
H03K 700
H03K 301
H03K 1700

US Classification:

307269

Abstract:

A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal. Each of the delay cells increases or decreases propagation time through that delay cell in response to the adjustment signal, so as to cause a time required for the logic state to propagate through all of the delay cells to be equal to a period of the clock signal.