Michael D Mcmahon

US Patent:

8489860, Jul 16, 2013

Filed:

Dec 22, 1997

Appl. No.:

08/995606

Inventors:

Michael McMahon - Plano TX, US
Marion C. Lineberry - Dallas TX, US
Matthew A. Woolsey - Plano TX, US
Gerard Chauvel - Antibes, FR

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 9/30

US Classification:

712 34

Abstract:

A wireless data platform comprises a plurality of processors. Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler executed on one processor compiles code into native processing code for another processor. A dynamic cross linker links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

US Patent:

62827065, Aug 28, 2001

Filed:

Feb 10, 1998

Appl. No.:

9/021241

Inventors:

Gerard Chauvel - Antibes, FR
Marion C. Lineberry - Dallas TX
Matthew A. Woolsey - Plano TX
Michael McMahon - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01F 945

US Classification:

717 9

Abstract:

A cache memory architecture 50, which may be, for example, a set associative cache memory, has a cache controller (52) with an internal register for storing the address of the active line currently latched in the output buffer of the high speed cache data array (56) which stores the cached data values from the main memory. If a memory access request specifies an address which would be contained in the active line, the cache look-up mechanisms are disabled and the data is taken from the output buffer. The efficiency of the cache can be increased by linking a program to memory such that the number of cache lines used by one or more program loops are minimized.