Michael A Minter

US Patent:

7290194, Oct 30, 2007

Filed:

Dec 17, 2004

Appl. No.:

11/016192

Inventors:

Donald Gabrielson - Rochester MN, US
Todd Youngman - Rochester MN, US
John Nordman - Rochester MN, US
Michael A. Minter - Bowling Green KY, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 31/28

US Classification:

714742

Abstract:

A tool for facilitating automatic test pin assignment for a programmable platform device including a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable platform device, a process configured to receive user specifications for IOs and a process for performing dynamic test pin reassignment in response to the user specifications.

US Patent:

8336012, Dec 18, 2012

Filed:

Apr 9, 2009

Appl. No.:

12/421198

Inventors:

Randall P. Fry - Greenville NC, US
Michael A. MInter - Bowling Green KY, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

716113, 716108, 716111, 716112, 716134, 703 19

Abstract:

A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.

US Patent:

20040268279, Dec 30, 2004

Filed:

Jun 24, 2003

Appl. No.:

10/602937

Inventors:

Nicholas Oleksinski - Northville MI, US
Michael Minter - Bowling Green KY, US

Assignee:

LSI LOGIC CORPORATION

International Classification:

G06F009/45

US Classification:

716/006000

Abstract:

A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.

US Patent:

20070044056, Feb 22, 2007

Filed:

Aug 16, 2005

Appl. No.:

11/204514

Inventors:

Michael Minter - Bowling Green KY, US
Donald Amundson - New Prague MN, US
Donald Gabrielson - Rochester MN, US

International Classification:

G06F 17/50

US Classification:

716008000

Abstract:

A design tool includes a first module, a second module, a third module and a fourth module. The first module may be configured to select a platform for implementing an integrated circuit design in response to input from a user. The second module may be configured to select a macro block to be placed on the platform in response to input from the user. A description of the macro block may be configured to indicate whether the macro block has connectivity placement data. The third module may be configured to determine whether the macro block has the connectivity placement data based on the description of the macro block. The fourth module may be configured to automatically place the macro block on the platform based on the connectivity placement data, when the description of the macro block indicates the connectivity placement data is present.