Michael A Moretti

US Patent:

7239645, Jul 3, 2007

Filed:

Sep 9, 2003

Appl. No.:

10/659535

Inventors:

Salil Suri - Fremont CA, US
David Geddes - Fremont CA, US
Scott Furey - Cupertino CA, US
Michael Moretti - Saratoga CA, US
Thomas Wu - Pleasanton CA, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370412, 37039553, 37039564, 3703957, 37039571, 37039572, 710 52, 710 53, 710 55, 710 56, 710 57

Abstract:

A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

US Patent:

20040120333, Jun 24, 2004

Filed:

May 8, 2003

Appl. No.:

10/434872

Inventors:

David Geddes - Fremont CA, US
Michael Moretti - Saratoga CA, US
Salil Suri - Fremont CA, US
Scott Furey - Cupertino CA, US
Thomas Wu - Pleasanton CA, US

International Classification:

H04L012/56

US Classification:

370/411000, 370/465000, 370/400000

Abstract:

A method and apparatus for controlling information flow through a protocol bridge is disclosed. In one embodiment, circular queues in dual port memory are used for passing frame header information and control information between the hardware and a processor. In one embodiment, a ‘control bit’ in each element in the dual port memory serves as a signaling mechanism for passing control of the circular queue elements between the hardware and the software. In another embodiment, a ‘skip bit’ is used to simplify error handling by enabling the circular queue elements to be processed in a particular order even under error conditions.

US Patent:

20040151191, Aug 5, 2004

Filed:

May 23, 2003

Appl. No.:

10/445105

Inventors:

Thomas Wu - Pleasanton CA, US
David Geddes - Fremont CA, US
Salil Suri - Fremont CA, US
Scott Furey - Cupertino CA, US
Michael Moretti - Saratoga CA, US

International Classification:

H04L012/28
G06F015/16
H04L012/56

US Classification:

370/401000, 709/249000, 709/236000

Abstract:

A method and apparatus for processing data frames using a networking device is disclosed. In one embodiment, a packet-over-SONET (POS) frame containing an encapsulated Fibre Channel frame is received by a protocol bridge. The POS header may then be stripped off and placed into a queue, while the encapsulated raw FC frame may be placed into a buffer of the protocol bridge. Hardware logic may then be used to generate and transmit a Fibre Channel frame using the previously encapsulated raw FC frame from the buffer. In another embodiment, a raw Fibre Channel data frame by the protocol bridge and then encapsulated into a POS frame and sent out on a POS interface. In one embodiment, this process may be carried in either a raw frame mode or an interleaved mode.