Michael Regan Moriarty

US Patent:

6446149, Sep 3, 2002

Filed:

Mar 3, 1998

Appl. No.:

09/033964

Inventors:

Michael P. Moriarty - Spring TX
Thomas J. Bonola - Tomball TX
Craig A. Walrath - Spring TX
Charles N. Shaver - Cypress TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1516

US Classification:

710110, 710108, 709213, 709216, 711152, 711163

Abstract:

A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell. Ownership of the semaphore memory cell is thus achieved using a single operation by a busmaster.

US Patent:

6538662, Mar 25, 2003

Filed:

May 23, 2001

Appl. No.:

09/862510

Inventors:

Michael P. Moriarty - Spring TX

Assignee:

Duke University - Durham NC

International Classification:

G06G 536

US Classification:

345605, 345549, 345545

Abstract:

In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

US Patent:

7046308, May 16, 2006

Filed:

Nov 13, 1998

Appl. No.:

09/191629

Inventors:

Thanh T. Tran - Houston TX, US
Michael P. Moriarty - Spring TX, US
Giang H. Dao - Houston TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04N 7/01
G06F 13/16

US Classification:

348725, 345521

Abstract:

A digital television/local bus interface logic supports handling of digital television (DTV) data with non-tearing. The interface logic provides a dual frame buffer DTV architecture in which a pair of DTV/local bus frame buffers alternate functions: one frame buffer stores incoming DTV data and the other frame buffer stores the outgoing DTV data. When a refresh of a display device reaches a programmed position of the display device, the interface logic determines which frame buffer is being updated by the incoming DTV data. The outgoing DTV data is then read from an opposite frame buffer and transmitted to the display device. The interface logic receives a horizontal sync signal and a vertical sync signal from the graphics controller for monitoring refresh of the display device. The interface logic also provides an architecture for transferring decoded DTV data over a local bus to the graphics controller.

US Patent:

59387394, Aug 17, 1999

Filed:

Mar 5, 1997

Appl. No.:

8/811587

Inventors:

Michael J. Collins - Tomball TX
Gary W. Thome - Tomball TX
Michael P. Moriarty - Spring TX
Jens K. Ramsey - Houston TX
John E. Larson - Katy TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300
G06F 1314

US Classification:

710 5

Abstract:

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

US Patent:

57014337, Dec 23, 1997

Filed:

Sep 30, 1996

Appl. No.:

8/727178

Inventors:

Michael P. Moriarty - Spring TX
John E. Larson - Katy TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1200
G06F 1300

US Classification:

395481

Abstract:

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

US Patent:

55353959, Jul 9, 1996

Filed:

Oct 2, 1992

Appl. No.:

7/955499

Inventors:

Roger E. Tipley - Houston TX
Michael Moriarty - Spring TX
Mark Taylor - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

395729

Abstract:

Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2). times. (n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master.

US Patent:

61920827, Feb 20, 2001

Filed:

Nov 13, 1998

Appl. No.:

9/191917

Inventors:

Michael P. Moriarty - Spring TX
Thanh T. Tran - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

H04B 166

US Classification:

37524026

Abstract:

A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.

US Patent:

60761393, Jun 13, 2000

Filed:

Sep 30, 1997

Appl. No.:

8/940914

Inventors:

Mark W. Welker - Spring TX
Thomas J. Bonola - Tomball TX
Michael P. Moriarty - Spring TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1316

US Classification:

711104

Abstract:

A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.