Michael I Morrison

US Patent:

6370639, Apr 9, 2002

Filed:

Oct 10, 1998

Appl. No.:

09/169482

Inventors:

Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA
Guillermo Juan Rozas - Los Gatos CA

Assignee:

Institute for the Development of Emerging Architectures L.L.C. - Cupertino CA

International Classification:

G06F 9312

US Classification:

712222, 712224, 712228, 712235, 712239

Abstract:

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

US Patent:

6578059, Jun 10, 2003

Filed:

Oct 10, 1998

Appl. No.:

09/169669

Inventors:

Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 748

US Classification:

708496, 712222

Abstract:

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

US Patent:

62125397, Apr 3, 2001

Filed:

Oct 10, 1998

Appl. No.:

9/169483

Inventors:

Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA

Assignee:

Institute for the Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 700

US Classification:

708495

Abstract:

A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

US Patent:

61516694, Nov 21, 2000

Filed:

Oct 10, 1998

Appl. No.:

9/169481

Inventors:

Jerome C. Huck - Palo Alto CA
Peter Markstein - Woodside CA
Glenn T. Colon-Bonet - Fort Collins CO
Alan H. Karp - Palo Alto CA
Roger Golliver - Beaverton OR
Michael Morrison - Sunnyvale CA
Gautam B. Doshi - Sunnyvale CA
Guillermo Juan Rozas - Los Gatos CA

Assignee:

Institute For The Development of Emerging Architectures, L.L.C. - Cupertino CA

International Classification:

G06F 1500

US Classification:

712222

Abstract:

A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

US Patent:

20220374288, Nov 24, 2022

Filed:

Oct 30, 2020

Appl. No.:

17/771686

Inventors:

- Sunnyvale CA, US
Michael Edwin JAMES - San Carlos CA, US
Michael MORRISON - Sunnyvale CA, US
Sean LIE - Los Altos CA, US
Gary R. LAUTERBACH - Los Altos CA, US
Stanislav FUNIAK - St Lucia, Queensland, AU

International Classification:

G06F 9/54
G06F 9/50

Abstract:

Techniques in distributed placement of linear operators for accelerated deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets. The routing is in accordance with virtual channel specifiers of the wavelets and controlled by routing configuration information of the router. A software stack determines distributed placement of linear operators based on a description of a neural network. The determined placement is used to configure the routers including usage of the respective colors. The determined placement is used to configure the compute elements including the respective programmed instructions each is configured to execute.

US Patent:

20230125522, Apr 27, 2023

Filed:

Oct 30, 2020

Appl. No.:

17/771606

Inventors:

- Sunnyvale CA, US
Michael Edwin JAMES - San Carlos CA, US
Michael MORRISON - Sunnyvale CA, US
Sean LIE - Los Altos CA, US
Gary R. LAUTERBACH - Los Altos CA, US
Stanislav FUNIAK - St Lucia, Queensland, AU

International Classification:

G06N 3/063

Abstract:

Techniques in optimized placement for efficiency for accelerated deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets. The routing is in accordance with virtual channel specifiers of the wavelets and controlled by routing configuration information of the router. A software stack determines optimized placement based on a description of a neural network. The determined placement is used to configure the routers including usage of the respective colors. The determined placement is used to configure the compute elements including the respective programmed instructions each is configured to execute.

US Patent:

20230071424, Mar 9, 2023

Filed:

Oct 29, 2020

Appl. No.:

17/771410

Inventors:

- Sunnyvale CA, US
Michael Edwin JAMES - San Carlos CA, US
Michael MORRISON - Sunnyvale CA, US
Sean LIE - Los Altos CA, US
Gary R. LAUTERBACH - Los Altos CA, US
Stanislav FUNIAK - St Lucia, Queensland, AU

International Classification:

G06N 3/063
G06N 3/04
G06K 9/62

Abstract:

Techniques in placement of compute and memory for accelerated deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element comprises a compute element to execute programmed instructions using the data and a router to route the wavelets. The routing is in accordance with virtual channel specifiers of the wavelets and controlled by routing configuration information of the router. A software stack determines placement of compute resources and memory resources based on a description of a neural network. The determined placement is used to configure the routers including usage of the respective colors. The determined placement is used to configure the compute elements including the respective programmed instructions each is configured to execute.

US Patent:

20200380370, Dec 3, 2020

Filed:

Apr 13, 2018

Appl. No.:

16/603789

Inventors:

- Los Altos CA, US
Michael Edwin JAMES - San Carlos CA, US
Michael MORRISON - Sunnyvale CA, US
Gary R. LAUTERBACH - Los Altos CA, US
Srikanth AREKAPUDI - Santa Clara CA, US

International Classification:

G06N 3/08
G06N 3/063
G06F 7/499
G06F 7/58

Abstract:

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements comprising a portion of a neural network accelerator performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has a respective floating-point unit enabled to perform stochastic rounding, thus in some circumstances enabling reducing systematic bias in long dependency chains of floating-point computations. The long dependency chains of floating-point computations are performed, e.g., to train a neural network or to perform inference with respect to a trained neural network.