Michael Ramon Perez

Address:

9922 Hustead St, Dallas, TX 75217

VIN:

1FTRW12W77KC57877

Make:

FORD

Model:

F-150

Year:

2007

Address:

725 Middle Gln Dr, Garland, TX 75043

Phone:

(214)4401908

VIN:

3GCEC14X37G253605

Make:

CHEVROLET

Model:

SILVERADO C1500

Year:

2007

US Patent:

6473814, Oct 29, 2002

Filed:

May 3, 1999

Appl. No.:

09/303635

Inventors:

Michael Edward Lyons - Round Rock TX
Sean Michael McNeal - Austin TX
Michael Anthony Perez - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 35, 710 8, 710 33

Abstract:

A method and system for choosing an optimal PCI adapter burst length is disclosed. The optimal burst length is automatically determined by the adapter configuration feature of AIX software using a cache-line size of a PCI bridge and the latency timer value of the target PCI adapter as inputs. The method also provides for a user to be able to override the software-calculated setting.

US Patent:

6658599, Dec 2, 2003

Filed:

Jun 22, 2000

Appl. No.:

09/599182

Inventors:

Stephen Dale Linam - Austin TX
Michael Anthony Perez - Cedar Park TX
Louis Gabriel Rodriguez - Austin TX
Mark Walz Wenning - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 25, 714 44

Abstract:

A method, system, and apparatus for managing a failed input/output adapter within a data processing system is provided. In one embodiment, an operating system handler receives an indication that one of a plurality of input/output adapters has failed. The operating system handler consults an error log to determine which input/output adapter has failed. Once the bad input/output adapter has been determined, the operating system handler disables the bad input/output adapter and deallocates any processes bound for the bad input/output adapter without powering down the data processing system. A user is then notified of the bad input/output adapter so that the bad input/output adapter can be replaced. The input/output adapter may be replaced without powering down the data processing system. Once the bad input/output adapter has been replace, the new input/output adapter is enabled.

US Patent:

6662318, Dec 9, 2003

Filed:

Aug 10, 2000

Appl. No.:

09/637314

Inventors:

Irving Guwor Baysah - Austin TX
Michael Anthony Perez - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 48, 714 25, 714 26

Abstract:

A method, system, and apparatus for monitoring errors within a data processing system is provided. In one embodiment an error notification system receives an indication of notification conditions and actions from a user. The system then searches for the specified conditions. Responsive to the occurrence of the specified condition, the system performs specified actions and sends a notification to a user. The specified actions may include, for example, rebooting the computer or generating a web page of information regarding the occurrence of the condition. The notification may be sent to a user via, for example, e-mail.

US Patent:

6662320, Dec 9, 2003

Filed:

Jul 20, 2000

Appl. No.:

09/620724

Inventors:

Rafael Graniello Cabezas - Austin TX
Robert George Kovacs - Austin TX
Michael Anthony Perez - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 1000

US Classification:

714 56, 714 24, 710302

Abstract:

A method and an apparatus is presented for preventing an adapter card that has been reset from issuing spurious error signals due to the fact it is not synchronized with the system at the time it comes out of reset. To prevent spurious errors, the data processing issues a command to the adapter card that is to be reset that disables error checking before the reset command is sent. The reset command is sent next. After the adapter card completes the reset operation, it notifies the system that the reset is completed. The adapter card waits until it receives a command from the system to re-enable error checking before it turns back on error checking. In this manner, the system can insure that error checking is only turned back on synchronously with other system activities so that spurious error signals are not generated.

US Patent:

6665753, Dec 16, 2003

Filed:

Aug 10, 2000

Appl. No.:

09/637317

Inventors:

Pat Allen Buckland - Austin TX
Michael Anthony Perez - Cedar Park TX
Kiet Anh Tran - Cedar Park TX
Adalberto Guillermo Yanes - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300

US Classification:

710 52, 710 36, 710 54, 710 65, 709 24

Abstract:

A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.

US Patent:

6834363, Dec 21, 2004

Filed:

Mar 22, 2001

Appl. No.:

09/815543

Inventors:

Christopher Harry Austen - Austin TX
Michael Anthony Perez - Cedar Park TX
Mark Walz Wenning - Cedar Park TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 44, 714 26

Abstract:

A method for prioritizing bus errors for a computing system is provided. A subsystem test is executed on a first subsystem from a plurality of subsystems on a bus system, wherein the subsystem test on the bus system is specific to the first bus subsystem. An output is received in response to executing the subsystem test. In response to the output indicating an error on the first subsystem, a severity level is assessed based on the error. For all subsystems from the plurality of subsystems on the bus system, a subsystem test is executed on each remaining subsystem, wherein each subsystem test on the bus system is specific to each remaining subsystem. An output is received in response to executing each subsystem test. In response to the output indicating an error on any of the remaining subsystems, a severity level is assessed based on the error.

US Patent:

6976191, Dec 13, 2005

Filed:

Mar 7, 2002

Appl. No.:

10/093433

Inventors:

Alongkorn Kitamorn - Austin TX, US
Ashwini Kulkarni - Austin TX, US
Gordon D. McIntosh - Austin TX, US
Kanisha Patel - Cedar Park TX, US
Michael Anthony Perez - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F011/00

US Classification:

714 43, 714 44, 714 56

Abstract:

A method, apparatus, and computer instructions for processing errors in a hierarchical input/output sub-system having an input/output bridge with a plurality of hardware devices in a level below the bridge. A value is read from a selected register to form a read value in response to detecting an error. The selected register is reset. Each bit in the read value associated with the error is cleared to form a cleared value. The cleared value is written into the selected register such that errors occurring since the register was cleared are preserved. The error registers below the bridge are scanned in response to an absence of an error being detected in a bridge within the input/output sub-system. A determination is made as to whether the error has previously occurred in response to a presence of an error being found by scanning the registers below the bridge. The error is reported in response to an absence of a determination that the error has previously occurred.

US Patent:

7103808, Sep 5, 2006

Filed:

Apr 10, 2003

Appl. No.:

10/411464

Inventors:

Alongkorn Kitamorn - Austin TX, US
Ashwini Kulkarni - Austin TX, US
Gordon D. McIntosh - Austin TX, US
Michael Anthony Perez - Cedar Park TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00
G06F 11/07

US Classification:

714 44, 714 43, 714 9, 714 48

Abstract:

A method, apparatus, and computer instructions for reporting errors occurring in a data processing system. Responsive to an error occurring in a host bridge in the data processing system, a determination is made as to whether a device required for generating an error report is located below the host bridge. Responsive to the device required for generating an error report being located below a host bridge, the host bridge is isolated from other portions of the data processing system, wherein only a processor analyzing the error is able to access the host bridge. An error reporting process is performed. The error reporting process is able to access the host bridge and the device.