Michael F Shaw

US Patent:

8059607, Nov 15, 2011

Filed:

Jun 26, 2003

Appl. No.:

10/607329

Inventors:

Michael J. Shaw - El Dorado Hills CA, US
Daniel R. Dillon - Fair Oaks CA, US
Graham Smith - El Dorado Hills CA, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H04Q 7/00
H04L 27/04
H04B 1/02

US Classification:

370334, 370329, 370338, 375295, 455 91, 455101

Abstract:

A spatial transmit diversity method includes transmitting data at a selected rate from a first antenna and awaiting an acknowledgement indicating successful receipt by the receiving terminal of the data transmitted at the selected rate from the first antenna. The data are then transmitted at the selected rate from a second antenna upon failure to receive an acknowledgement of successful receipt by the receiving terminal of the data transmitted at the selected rate from the first antenna within a predetermined time interval.

US Patent:

20140030981, Jan 30, 2014

Filed:

Jul 27, 2012

Appl. No.:

13/559745

Inventors:

MICHAEL JOSEPH SHAW - Granite Bay CA, US
JONATHAN LEE KENNEDY - Grass Valley CA, US
DARRELL LEE LIVEZEY - Auburn CA, US
JOY LASKAR - Los Altos CA, US

Assignee:

Tahoe RF Semiconductor, Inc. - Auburn CA

International Classification:

H04B 1/10

US Classification:

455 631, 455296, 4552341

Abstract:

A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.

US Patent:

20200409561, Dec 31, 2020

Filed:

Jun 25, 2019

Appl. No.:

16/451841

Inventors:

- Cupertino CA, US
Michael Shaw - Colorado Springs CO, US

International Classification:

G06F 3/06

Abstract:

In a data storage system, latency optimization can be practiced by logging a plurality of data accesses to a memory in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory. The register may be analyzed with a system module to predict a command execution latency value for the plurality of data accesses that can be used to generate a deterministic data access sequence with the system module. A queue of data accesses can then be reorganized from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.

US Patent:

20200409874, Dec 31, 2020

Filed:

Jun 25, 2019

Appl. No.:

16/451864

Inventors:

- Cupertino CA, US
Michael Shaw - Colorado Springs CO, US
Thomas V. Spencer - Fort Collins CO, US
Yalan Liu - Longmont CO, US
Sarvani Reddy Kolli - Longmont CO, US

International Classification:

G06F 13/16
G06F 12/02
G06F 9/50
G06F 11/07

Abstract:

A data storage system can organize a semiconductor memory into a first data set and a second data set with a first queue populated with a first data access request from a host. An assignment of an arbitration weight to the first queue with an arbitration circuit corresponds with the first queue being skipped during a deterministic window based on the arbitration weight.

US Patent:

20160149540, May 26, 2016

Filed:

Nov 20, 2015

Appl. No.:

14/948052

Inventors:

- San Jose CA, US
Michael SHAW - Granite Bay CA, US

International Classification:

H03F 1/02
H03G 3/30
H03F 3/08

Abstract:

The present invention relates to a linear, high sensitivity, high speed trans-impedance amplifier (TIA) Which allows a large dynamic range of input current up to very large values, maintains high linearity and keeps constant output voltage, maintains the same frequency response across the full gain control range, provides very high input sensitivity and large bandwidth, and allows input current monitoring without affecting input sensitivity. In other words, the novel circuit disclosed herein provides for the feedback path to maintain the same level of feedback even while the output signal is varied. This allows a wide and stable bandwidth, as well as a monitor to be placed in the TIA.