Michael Richard Shaw

US Patent:

20200409561, Dec 31, 2020

Filed:

Jun 25, 2019

Appl. No.:

16/451841

Inventors:

- Cupertino CA, US
Michael Shaw - Colorado Springs CO, US

International Classification:

G06F 3/06

Abstract:

In a data storage system, latency optimization can be practiced by logging a plurality of data accesses to a memory in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory. The register may be analyzed with a system module to predict a command execution latency value for the plurality of data accesses that can be used to generate a deterministic data access sequence with the system module. A queue of data accesses can then be reorganized from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.

US Patent:

20200409874, Dec 31, 2020

Filed:

Jun 25, 2019

Appl. No.:

16/451864

Inventors:

- Cupertino CA, US
Michael Shaw - Colorado Springs CO, US
Thomas V. Spencer - Fort Collins CO, US
Yalan Liu - Longmont CO, US
Sarvani Reddy Kolli - Longmont CO, US

International Classification:

G06F 13/16
G06F 12/02
G06F 9/50
G06F 11/07

Abstract:

A data storage system can organize a semiconductor memory into a first data set and a second data set with a first queue populated with a first data access request from a host. An assignment of an arbitration weight to the first queue with an arbitration circuit corresponds with the first queue being skipped during a deterministic window based on the arbitration weight.