Michael K Sheehan

US Patent:

48334189, May 23, 1989

Filed:

Sep 1, 1988

Appl. No.:

7/239302

Inventors:

John J. Quintus - Buena Park CA
Michael S. Sheehan - Santa Ana CA

Assignee:

Archive Corporation - Costa Mesa CA

International Classification:

H03F 345

US Classification:

330 9

Abstract:

An apparatus for nullifying the differential output offset voltage between the outputs of a differential amplifier and for setting the DC levels of the outputs to a known reference voltage includes a circuit which cross-couples the opposing AC output signals to obtain only the DC components of each signal. The apparatus further includes a first operational amplifier to generate a compensation voltage from the DC components of the outputs of the differential amplifier proportional to the amount of offset between the DC components of the outputs of the differential amplifier. The compensation voltage is fed back to the offset control inputs of the differential amplifier to reduce the differential offset voltage to substantially zero volts. The apparatus further includes a dual voltage divider network having a second operational amplifier that supplies a variable reference voltage to one terminal of each leg of the voltage divider network. The outputs of the differential amplifier each provided to a respective other terminal of the dual voltage divider network.

US Patent:

51722801, Dec 15, 1992

Filed:

Oct 26, 1989

Appl. No.:

7/428501

Inventors:

John J. Quintus - Buena Park CA
Michael S. Sheehan - Laguna Hills CA
Tuong M. Vu - El Toro CA

Assignee:

Archive Corporation - Costa Mesa CA

International Classification:

G11B 2736

US Classification:

360 31

Abstract:

An apparatus and a method for calibrating the write current applied to a write head (110, 114) in a tape drive (100) finds the peak value of the write current applied to the tape head (110, 114) (i. e. , the write current value providing the maximum read voltage amplitude on a tape (104)) by indirectly measuring the voltage sensed by a read head (112, 115). The apparatus includes a digital write current control circuit (170, 160) that applies a write current having a magnitude responsive to a digital write current value. An amplifier (190) in a read circuit (180, 182, 184, 190, 196) has a gain responsive to a digital read gain value. The method includes the steps of sampling the output of a pattern detector (146) (e. g. , a gap detector) as the digital read gain value is adjusted for each of a number of digital write current data values applied to the write current control circuit (170, 160). The digital read gain value is adjusted to provide a predetermined range of the number of samples wherein the pattern corresponds to a predetermined pattern.