Michael C Smits

US Patent:

7491660, Feb 17, 2009

Filed:

Oct 17, 2007

Appl. No.:

11/873721

Inventors:

Richard A. Conti - Katohah NY, US
Ronald P. Bourque - Wappingers Falls NY, US
Nancy R. Klymko - Hopewell Junction NY, US
Anita Madan - Danbury NY, US
Michael C. Smits - Poughkeepsie NY, US
Roy H. Tilghman - Stormville NY, US
Kwong Hon Wong - Wappingers Falls NY, US
Daewon Yang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY
Novellus Systems. Inc. - San Jose CA

International Classification:

H01L 21/31
H01L 21/469
C23C 16/00
C23C 14/10
C23C 14/00

US Classification:

438791, 438792, 42725523, 42725526, 42725527

Abstract:

A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2. 8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13. 56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

US Patent:

7804136, Sep 28, 2010

Filed:

Oct 19, 2007

Appl. No.:

11/875217

Inventors:

Richard A. Conti - Katonah NY, US
Ronald P. Bourque - Wappingers Falls NY, US
Nancy R. Klymko - Hopewell Junction NY, US
Anita Madan - Danbury NY, US
Michael C. Smits - Poughkeepsie NY, US
Roy H. Tilghman - Stormville NY, US
Kwong Hon Wong - Wappingers Falls NY, US
Daewon Yang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/62

US Classification:

257369, 257E21293

Abstract:

A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2. 8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13. 56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

US Patent:

20070007548, Jan 11, 2007

Filed:

Jul 6, 2005

Appl. No.:

11/160705

Inventors:

Richard Conti - Katonah NY, US
Ronald Bourque - Wappingers Falls NY, US
Nancy Klymko - Hopewell Junction NY, US
Anita Madan - Danbury CT, US
Michael Smits - Poughkeepsie NY, US
Roy Tilghman - Stormville NY, US
Kwong Wong - Wappingers Falls NY, US
Daewon Yang - Hopewell Junction NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
NOVELLUS SYSTEMS INC. - San Jose CA

International Classification:

H01L 21/8234
H01L 27/10
H01L 21/31

US Classification:

257202000, 438197000, 438199000, 438791000

Abstract:

A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.