Michael A Snyder

US Patent:

6499116, Dec 24, 2002

Filed:

Mar 31, 1999

Appl. No.:

09/282694

Inventors:

Charles Philip Roth - Austin TX
Michael Dean Snyder - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY
Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1100

US Classification:

714 39, 711146

Abstract:

Data stream touch instructions are software-directed asynchronous prefetch instructions that can improve the performance of a system. Ideally, such instructions are used in perfect synchronization with the actual memory fetches that are trying to speed up. In practical situations, it is difficult to predict ahead of time all side effects of these instructions and memory access latency/throughput during execution of any large program. Incorrect usage of such instructions can cause degraded performance of the system. Thus, it is advantageous to measure the performance of such instructions.

US Patent:

6581140, Jun 17, 2003

Filed:

Jul 3, 2000

Appl. No.:

09/609749

Inventors:

Steven C. Sullivan - Austin TX
Michael D. Snyder - Austin TX
Magnus K. Bruce - Cedar Park TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200

US Classification:

711128, 711204, 711213

Abstract:

A system provides a method and apparatus for accessing information in a cache in a data processing system. The system optimizes a speed-critical path within the cache system by using a prediction scheme. The prediction scheme subdivides the address range of address bits and compares the portions separately. A comparison of a critical portion of the address, along with a prediction bit, are used to generate a prediction.

US Patent:

6785772, Aug 31, 2004

Filed:

Apr 26, 2002

Appl. No.:

10/132918

Inventors:

Suresh Venkumahanti - Austin TX
Michael Dean Snyder - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1200

US Classification:

711137, 711128, 711158, 711213, 712207

Abstract:

A data processing system ( ) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache ( ). When attempting to be backward compatible with previously written code, sometimes performing this instruction can result in attempting to prefetch redundant data by prefetching the same data twice. In order to prevent this, the parameters of the instruction are analyzed to determine if such redundant data will be prefetched. If so, then the parameters are altered to avoid prefetching redundant data. In some of the possibilities for the parameters of the instruction, the altering of the parameters requires significant circuitry so that an alternative approach is used. This alternative but slower approach, which can be used in the same system with the first approach, detects if the line of the cache that is currently being requested is the same as the previous request. If so, the current request is not executed.

US Patent:

6842822, Jan 11, 2005

Filed:

Apr 5, 2002

Appl. No.:

10/117610

Inventors:

Michael D. Snyder - Austin TX, US
Magnus K. Bruce - Cedar Park TX, US
Jamshed Jalal - Cedar Park TX, US
Thomas A. Hoy - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1200

US Classification:

711118, 711141, 711142, 711143, 711144, 711145

Abstract:

A system () uses shared resources () to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (). A reload buffer () is used in conjunction with a cache () operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal () selectively enables the pushing of data into the cache () from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.

US Patent:

7069384, Jun 27, 2006

Filed:

Oct 14, 2004

Appl. No.:

10/965596

Inventors:

Michael D. Snyder - Austin TX, US
Magnus K. Bruce - Cedar Park TX, US
Jamshed Jalal - Cedar Park TX, US
Thomas A. Hoy - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/00

US Classification:

711118, 711141, 711144

Abstract:

A system () uses shared resources () to perform conventional load/store operations, to preload custom data from external sources, and to efficiently manage error handling in a cache (). A reload buffer () is used in conjunction with a cache () operating in a write-through mode to permit lower level memory in the system to operate in a more efficient write-back mode. A control signal () selectively enables the pushing of data into the cache () from an external source. The control signal utilizes one or more attribute fields that provide functional information and define memory characteristics.

US Patent:

7506105, Mar 17, 2009

Filed:

May 2, 2005

Appl. No.:

11/120288

Inventors:

Hassan F. Al-Sukhni - Austin TX, US
James C. Holt - Austin TX, US
Matt B. Smittle - Allen TX, US
Michael D. Snyder - Austin TX, US
Brian C. Grayson - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 12/06
G06F 9/34

US Classification:

711137, 711216, 711217, 712207

Abstract:

Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

US Patent:

7675806, Mar 9, 2010

Filed:

May 17, 2006

Appl. No.:

11/435942

Inventors:

Bradford Hunter - Austin TX, US
David Burnett - Austin TX, US
Troy Cooper - Austin TX, US
Prashant Kenkare - Austin TX, US
Andrew Russell - Austin TX, US
Shayan Zhang - Austin TX, US
Michael Snyder - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 5/14

US Classification:

365227, 365226, 365228, 365229, 365154

Abstract:

A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.

US Patent:

7681021, Mar 16, 2010

Filed:

Sep 28, 2006

Appl. No.:

11/536173

Inventors:

Sergio Schuler - Austin TX, US
Michael D. Snyder - Austin TX, US
Leick D. Robinson - Round Rock TX, US
David M. Thompson - Arlington TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/00
G06F 1/32

US Classification:

712238, 713324

Abstract:

A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.