Michael A Stapleton

US Patent:

6462438, Oct 8, 2002

Filed:

Sep 27, 2000

Appl. No.:

09/670751

Inventors:

Michael A. Stapleton - Portland OR
Bernard W. Boland - Hillsboro OR
Jeffery J. Olsen - Banks OR
John A. Dickerson - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01H 3500

US Classification:

307130, 307126

Abstract:

A method includes converting a first voltage into a second voltage. The second voltage is routed to a power supply line when the second voltage exceeds a first predefined threshold, and the second voltage is isolated from the power supply line when the first voltage decreases below a second predefined voltage.

US Patent:

6472899, Oct 29, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751051

Inventors:

Edward P. Osburn - Folsom CA
Michael A. Stapleton - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128

US Classification:

324765, 702118

Abstract:

The present invention provides a method or process for determining a load line based variable voltage input for an Integrated Circuit (IC) product. More particularly, the present invention provides a method/process for determining a variable load line that defines voltage input (Vcc) as a function of current draw (Icc) for an IC product. In one embodiment, the method includes defining a minimum voltage relative to a reference voltage level for an IC product at a maximum current draw Icc of the IC product. A maximum voltage relative to the reference voltage level for the IC product, at a minimum current draw Icc of the IC product, is also defined. Next, a load line based upon the maximum and minimum voltages and current draws, respectively, is calculated. The load line defines the voltage requirements for the IC product as a function of current draw Icc.

US Patent:

6523128, Feb 18, 2003

Filed:

Aug 31, 1999

Appl. No.:

09/387423

Inventors:

Michael Stapleton - Portland OR
Philip Doberenz - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 126

US Classification:

713330, 713324, 713340

Abstract:

A computer receives a sleep signal that instructs the computer to enter a sleeping state in which stand-by power from a power source is needed. The computer generates a control signal that initiates delivery of stand-by power from the power source in connection with the computers entering the sleeping state. The control signal is asserted in at least one situation in which the sleep signal is asserted, and the control signal is not asserted in at least one other situation.

US Patent:

6538888, Mar 25, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/964476

Inventors:

Wen Wei - Beaverton OR
Michael A. Stapleton - Portland OR
Richard F. Guarnero - Scappose OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 720

US Classification:

361697, 165121, 415177, 2989003

Abstract:

A radial base heatsink is provided to dissipate heat from a heat source. Such a heatsink comprises a cylindrical core; and a plurality of cooling fins projecting outwardly from the cylindrical core and defining a series of channels in a substantially radial pattern with a fin orientation relative to a center line of the cylindrical core, for dissipating heat generated from a heat source, via the cylindrical core.

US Patent:

6574577, Jun 3, 2003

Filed:

Dec 13, 2000

Appl. No.:

09/735812

Inventors:

Michael A. Stapleton - Portland OR
Bernard W. Boland - Hillsboro OR
Jeffery J. Olsen - Banks OR
John A. Dickerson - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02H 700

US Classification:

702117, 713340

Abstract:

A system includes a processor, a voltage regulator and a circuit. The processor uses a first supply voltage to furnish a first indication of a second supply voltage to be received by the processor. The voltage regulator furnishes the second supply voltage in response to both the first indication and a second indication that the first supply voltage is valid. The circuit provides the second indication and regulates a timing of the second indication to prevent the voltage regulator from furnishing the second supply voltage until a predefined interval of time has elapsed after the first supply voltage becomes valid.

US Patent:

6661263, Dec 9, 2003

Filed:

Dec 26, 2000

Appl. No.:

09/745413

Inventors:

Bruce W. Rose - Aloha OR
Michael A. Stapleton - Portland OR
Jeffrey J. Olsen - Banks OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 406

US Classification:

327134, 327131

Abstract:

A voltage sequencer includes an input terminal and an output terminal and a control element connected between the input an output terminals. A capacitive element is connected between the output terminal and a first voltage and a resistive element is connected between the output terminal and a second voltage. The control element selectively controls charging and discharging of the capacitive element such that, upon the voltage at the input terminal increasing from the first voltage to a nominal value, the output terminal voltage increases to a nominal value in a first predetermined period of time and upon the voltage at the input terminal decreasing from the nominal value to the first voltage, the output terminal voltage decreases to the first voltage value in a second predetermined period of time, the first predetermined period of time being different from, for example, substantially greater than, the second predetermined period of time. The capacitive element may be a capacitor and the resistive element may be a resistor. The first voltage may be a ground potential while the second voltage may be a positive potential with respect to the first voltage.

US Patent:

6880076, Apr 12, 2005

Filed:

Jun 29, 2001

Appl. No.:

09/895062

Inventors:

Robert J. Greiner - Beaverton OR, US
Matthew Ma - Portland OR, US
Edward P. Osburn - Folsom CA, US
Michael Stapleton - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F015/177

US Classification:

713 1, 713100, 713300, 713400, 713500, 713600, 709221, 709222, 709232, 709400

Abstract:

Embodiments of the present invention describe a system and method for microprocessor power regulation. An appropriate amount of voltage is provided to a microprocessor based on a voltage identifier (VID) received by a voltage controller from the microprocessor via a serial communication line. A voltage identifier clock signal (VIDClock) is used for the timing of transmission and receipt of data/acknowledgement signals. A guard clock signal (VIDGuard) is provided via a separate guard clock line to prevent potential noise on the clock line from causing a clock signal misidentification, which could cause a wrong value to be received as the VID. VIDGuard is analyzed in relation to ViDClock to verify the value of the clock signal. To verify receipt of the VID data, a voltage identifier acknowledgement line (VIDAck) is transmitted from the voltage regulator to the microprocessor. The acknowledgement signal is checked by a two-part receipt verification, high-to-low and low-to-high.

US Patent:

7759918, Jul 20, 2010

Filed:

Jun 16, 2006

Appl. No.:

11/424844

Inventors:

Ole P. Moyer - Chandler AZ, US
Christopher J. Gass - Tempe AZ, US
Paul J. Harriman - Goodyear AZ, US
Benjamin M. Rice - Attleboro MA, US
Michael A. Stapleton - Scottsdale AZ, US

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

G05F 1/59
G05F 1/565

US Classification:

323272, 323284

Abstract:

A method for method for inhibiting thermal run-away in a multi-phase power converter at varying load transition rates. A multi-phase power converter having an on-time is provided and the frequency of the multi-phase power converter is adjusted so that a load step period and the on time of the multi-phase power converter are in a temporal relationship. Alternatively, a load step rate is inhibited from locking onto a phase current of the multi-phase power converter by suspending an oscillator signal. In accordance with another alternative, a load step rate is inhibited from locking onto a phase current of the multi-phase power converter by suspending an oscillator signal and dithering an input signal to the oscillator.