Michael F Terry

US Patent:

7503084, Mar 17, 2009

Filed:

Feb 25, 2005

Appl. No.:

11/066411

Inventors:

Michael Norman Terry - Southlake TX, US

International Classification:

A47C 19/00
A47D 7/00
A47C 31/00
A47C 23/00

US Classification:

5 8, 5 11, 5310, 52001, 5307

Abstract:

A mattress leveling system designed to provide individually adjustable mattress heights, where mattresses of different firmness and thickness can be integrated into one bed with a level sleep surfaces sharing a common plane and held juxtaposed. Each mattress or mattress set is securely supported within a frame assembly with independently height adjustable legs. Users can integrate individual mattresses, which provide adequate firmness to meet the needs and desires of each of the users, forming one bed system customized to provide optimal comfort for both partners. An advantage of this design provides users with the ability to integrate into one bed, commonly available standard or non-standard adult size mattresses of differing thickness from different manufacturers, taking advantage of the latest sleep comfort technologies available on the market. Another advantage is the ability to exchange one mattress of the integrated bed without affecting the other mattress. Further advantages are, the ability to level the mattresses on uneven flooring, and the ability to integrate an unlimited number of mattresses into one bed.

US Patent:

43862810, May 31, 1983

Filed:

Jan 15, 1981

Appl. No.:

6/273841

Inventors:

Michael B. Terry - Dallas TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

H03K 1708

US Classification:

307200B

Abstract:

A circuit (10) is provided for use in a telecommunications integrated circuit which has a memory for storing a telephone number. The circuit (10) essentially comprises a latch having differential nodes (22, 28). The circuit (10) serves to detect when the supply voltage provided between the supply terminals (12, 14) drops to a level which causes loss of the data stored in the integrated circuit memory. An output signal (PUC) is driven to a low state upon detection of loss of power. For a slow return of supply power the nodes (22, 28) are respectively pulled to low and high states by current leakage through diodes (30, 36, 38) connected to the power terminals (12, 14). For a rapid supply voltage transition the latch node (28) is pulled high by capacitive coupling through a diode (30). This serves to set the latch in the condition where the output node (22) is at a low state to indicate loss of power. After generation of the PUC signal in the low state, external circuitry provides a reset signal (. phi. sub.

US Patent:

44790970, Oct 23, 1984

Filed:

Dec 24, 1981

Appl. No.:

6/270528

Inventors:

David N. Larson - Carrollton TX
Jeffrey Ireland - Farmers Branch TX
Michael B. Terry - Carrollton TX

Assignee:

Mostek Corporation - Carollton TX

International Classification:

H03K 450

US Classification:

331111

Abstract:

A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input terminal (16) of the voltage comparator circuit (12) for generating a reference voltage. A delay circuit (50, 52) is coupled to an output terminal (42) of the voltage comparator circuit (12). A discharge device (54) is coupled to the delay circuit (50, 52) and to the capacitor (20) for discharging the capacitor (20). A switching device (40) is coupled to the output (42) of the voltage comparator circuit (12) and to the resistor divider network (30) for controlling the application of the reference voltage to voltage comparator circuit (12).

US Patent:

43596800, Nov 16, 1982

Filed:

May 18, 1981

Appl. No.:

6/278905

Inventors:

James R. Hellums - Carrollton TX
Michael B. Terry - Dallas TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

G05F 320

US Classification:

323313

Abstract:

A voltage reference circuit (10) produces a reference voltage at output terminals (66, 76). The output reference voltage is substantially independent of variations in the supply voltage, integrated circuit manufacturing processes and temperature. A current reference circuit (30, 32, 34, 36, 38, 56 and 84) produces constant emitter currents in bipolar transistors (40, 70). The V. sub. BE of the bipolar transistors (40, 70) is a stable reference due to the constant emitter current. The bipolar transistors (40, 70) are manufactured with similar geometries to eliminate dependence of the reference voltage upon bipolar processing variations. The V. sub. BE of the bipolar transistor (40) produces a reference current which is provided to the base terminal of bipolar transistor (70). The V. sub. BE of bipolar transistor (70) is further utilized to produce the output reference voltage. A temperature stabilization circuit (58, 82, 86, 90, 92 and 94) is provided with an opposite temperature coefficient from that of the bipolar transistors (40, 70).