Michael T Todd

US Patent:

6528736, Mar 4, 2003

Filed:

Jan 21, 1997

Appl. No.:

08/786494

Inventors:

Daniel Phillip Dailey - West Bloomfield MI
Jay DeAvis Baker - Dearborn MI
Achyuta Achari - Canton MI
Myron Lemecha - Dearborn MI
Michael George Todd - South Lyon MI

Assignee:

Visteon Global Technologies, Inc. - Dearborn MI

International Classification:

H01R 909

US Classification:

174261, 174255, 361772, 361809

Abstract:

Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.

US Patent:

6555015, Apr 29, 2003

Filed:

Nov 9, 2000

Appl. No.:

09/712838

Inventors:

Daniel Phillip Dailey - West Bloomfield MI
Jay DeAvis Baker - Dearborn MI
Achyuta Achari - Canton MI
Myron Lemecha - Dearborn MI
Michael George Todd - South Lyon MI

Assignee:

Visteon Global Technologies, Inc. - Dearborn MI

International Classification:

H01B 1300

US Classification:

216 17, 216 19

Abstract:

Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.

US Patent:

6740246, May 25, 2004

Filed:

Apr 17, 2001

Appl. No.:

09/836645

Inventors:

Andrew Zachary Glovatsky - Plymouth MI
Robert Edward Belke - West Bloomfield MI
Marc Alan Straub - Dearborn Heights MI
Michael George Todd - Anaheim Hills CA

Assignee:

Visteon Global Tech., Inc. - Dearborn MI

International Classification:

H01B 1300

US Classification:

216 18, 216 15, 29829, 29846

Abstract:

A method for making multi-layer electronic circuit boards having âblindâ type apertures which may be selectively and electrically grounded and further having selectively formed air bridges and/or crossover circuits.

US Patent:

59868848, Nov 16, 1999

Filed:

Jul 13, 1998

Appl. No.:

9/114315

Inventors:

Vivek Amir Jairazbhoy - Farmington Hills MI
Michael George Todd - South Lyon MI
Prathap Amerwai Reddy - Farmington Hills MI

Assignee:

Ford Motor Company - Dearborn MI

International Classification:

H05K 720

US Classification:

361700

Abstract:

There is disclosed herein a printed circuit board, one embodiment of which comprises: a dielectric substrate 10; a solid metallic heat sink 16 attached to or embedded within the substrate; a cavity 18 formed generally in the substrate, wherein at least one wall 20 of the cavity is defined by a surface 17 of the heat sink 16; a component mounting pad 14 disposed on the substrate proximate the cavity; a predetermined volume of electrically insulative liquid 22 contained within the cavity; and a thermally conductive member 24 embedded within the substrate, the member 24 being in direct thermal contact with each of the mounting pad 14 and the liquid 22.

US Patent:

57838674, Jul 21, 1998

Filed:

Nov 6, 1995

Appl. No.:

8/554181

Inventors:

Robert Edward Belke - W. Bloomfield MI
Bethany Walles - Birmingham MI
Michael G. Todd - South Lyon MI
Brian J. Hayden - Royal Oak MI

Assignee:

Ford Motor Company - Dearborn MI

International Classification:

H01L 2348
H01L 2352
H01L 2740

US Classification:

257783

Abstract:

In a method for reversible assembly of a semiconductor electronic flip-chip device to an electrical interconnecting substrate, a filled thermoplastic adhesive is interposed between an active face of the flip-chip device and a bond site on the substrate. Electrical connection is established between the flip-chip device and the substrate and, generally simultaneously, adhesive bonding between them is established via viscous flow of the filled thermoplastic adhesive above its glass transition temperature, followed by cooling of the adhesive. The adhesive can be reheated to free the flip-chip device of its adhesive bond to the substrate. The filled thermoplastic adhesive includes a low expansion filler in a binder matrix. In accordance with one aspect of the invention, the binder matrix is poly(aryl ether ketone) having the chemical formula ##STR1## where n is from 5 to 150 and R is selected from suitable divalent moieties. The filled thermoplastic adhesive can be interposed between the flip-chip device and the substrate as a preform or by other suitable method, such as syringe extrusion in a molten or viscous state.

US Patent:

57387974, Apr 14, 1998

Filed:

May 17, 1996

Appl. No.:

8/649377

Inventors:

Robert E. Belke - West Bloomfield MI
Michael G. Todd - South Lyon MI
Andrew Z. Glovatsky - Ypsilanti MI
Alice D. Zitzmann - Dearborn MI

Assignee:

Ford Global Technologies, Inc. - Dearborn MI

International Classification:

B44C 122
C23F 100

US Classification:

216 16

Abstract:

A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut. The molded circuit structure is then removed from the mold and the metallic foil is further etched to complete the forming of the circuit.

US Patent:

6326241, Dec 4, 2001

Filed:

Dec 29, 1997

Appl. No.:

8/999153

Inventors:

Robert Edward Belke - W. Bloomfield MI
Brian John Hayden - Royal Oak MI
Cuong Van Pham - Northville MI
Rosa Lynda Nuno - Canton MI
Michael George Todd - South Lyon MI

Assignee:

Visteon Global Technologies, Inc. - Dearborn MI

International Classification:

H01L 2144

US Classification:

438118

Abstract:

A solderless method for assembling a semiconductor electronic flip-chip device to an electrical interconnecting substrate including the steps of forming a plurality of raised electrical contacts and plurality of contact pads. The pads correspond in number and physical location with the electrical contacts. The pads and contact mate when brought together. A quantity of plastic material is interposed between the electrical device and substrate. The plastic material is heated so that it softens and flows. The electronic device and substrate are urged together. The urging step displaces the molten plastic material from between the contacts and pads. The contacts and pads are jointed directly without any adhesive, solder or conducive filler therebetween to electrically interconnect the electronic device and substrate. The plastic material is allowed to cool whereby the electronic device and substrate are adhesively bonded together and electrically interconnected.

US Patent:

59946482, Nov 30, 1999

Filed:

Mar 27, 1997

Appl. No.:

8/826461

Inventors:

Andrew Z. Glovatsky - Ypsilanti MI
Michael G. Todd - South Lyon MI
Cuong Van Pham - Northville MI

Assignee:

Ford Motor Company - Dearborn MI

International Classification:

H05K 332

US Classification:

174260

Abstract:

An electrical circuit assembly which requires no solder processing, including an electronic component having terminations arranged on at least one of its surfaces, and a molded curviplanar substrate having circuit traces thereon and a cavity formed therein, wherein the cavity substantially conforms in shape with the electronic component. Proximate the cavity is a plurality of electrical contacts, arranged in matched relation with the respective terminations of the electronic component, with at least one of the electrical contacts being connected to at least one of the circuit traces on the substrate. The cavity and electrical contacts are dimensioned such that an interference fit is provided between the component's terminations and the electrical contacts, such that the component is held within the cavity when the component is placed therein. The component is disposed in the cavity such that its terminations are in physical and electrical connection with their respective electrical contacts.