Michael H Trang

Device Test And Characterization And Metrology

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Location:

2921 Tollive Dr, San Jose, CA

Industry:

Electrical/Electronic Manufacturing

Work:

Intermolecular
Device Test and Characterization and Metrology Process
Vishay Siliconix Feb 2011 - Apr 2011
Engineering
Solexel Jan 2008 - Dec 2010
Senior Test and Characterization Development Engineer
Cadence Design Systems May 2002 - Jan 2008
Senior Test Engineer, Layout Designer
Micrel Semiconductor Jun 1999 - Mar 2002
Test Device Modeling Engineer

Education:

San Jose State University 2000 - 2000
Bachelors, Electronics Engineering Western Polytechnic University
Masters, Electronics Engineering

Skills:

R&D
Characterization
Design of Experiments
Failure Analysis
Semiconductors
Manufacturing
Process Simulation
Thin Films
Solar Energy
Test Equipment
Layout Tools
Process Engineering
Process Integration
Solar Pv
Test Chip Layout Structures
Product Development
Cadence Spectre
Cadence Virtuoso
Simulation Software
Cad
Autocad
Test Automation
Project Management
Ni Labview
Labwindows/Cvi
Programming
Cascade
Pvd
Coatings
Equipment Installation
Laboratory Equipment
Agile Methodolgy
Device Characterization
Semiconductor Device
Data Analysis

Languages:

English
Vietnamese
Italian

Michael Trang

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