Michael Giang Van

US Patent:

6465306, Oct 15, 2002

Filed:

Nov 28, 2000

Appl. No.:

09/723635

Inventors:

Mark T. Ramsbey - Sunnyvale CA
Jean Y. Yang - Sunnyvale CA
Hidehiko Shiraiwa - San Jose CA
Michael A. Van Buskirk - Saratoga CA
David M. Rogers - Sunnyvale CA
Ravi Sunkavalli - Santa Clara CA
Janet Wang - San Francisco CA
Narbeh Derhacobian - Belmont CA
Yider Wu - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

International Classification:

H01L 21336

US Classification:

438279, 438261, 438264, 438287, 438288, 438594, 438981

Abstract:

One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

US Patent:

6468865, Oct 22, 2002

Filed:

Nov 28, 2000

Appl. No.:

09/723653

Inventors:

Jean Y. Yang - Sunnyvale CA
Mark T. Ramsbey - Sunnyvale CA
Hidehiko Shiraiwa - San Jose CA
Michael A. Van Buskirk - Saratoga CA
David M. Rogers - Sunnyvale CA
Ravi Sunkavalli - Santa Clara CA
Janet Wang - San Francisco CA
Narbeh Derhacobian - Belmont CA
Yider Wu - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

International Classification:

H01L 21336

US Classification:

438262, 438257, 438261, 257314

Abstract:

One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

US Patent:

6492675, Dec 10, 2002

Filed:

Jan 16, 1998

Appl. No.:

09/008162

Inventors:

Michael A. Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2972

US Classification:

257314, 257316, 257318, 257321, 257328, 257344

Abstract:

A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

US Patent:

6493261, Dec 10, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795865

Inventors:

Darlene G. Hamilton - San Jose CA
Kulachet Tanpairoj - Palo Alto CA
Ravi Sunkavalli - Santa Clara CA
Narbeh Derhacobian - Belmont CA
Michael A. Van Buskirk - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518511, 36518533, 36518505

Abstract:

Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

US Patent:

6510082, Jan 21, 2003

Filed:

Oct 23, 2001

Appl. No.:

09/999869

Inventors:

Binh Q. Le - San Jose CA
Michael A. Van Buskirk - Saratoga CA
Santosh K. Yachareni - Santa Clara CA
Michael S. C. Chung - San Jose CA
Kazuhiro Kurihara - Sunnyvale CA
Shane Hollmer - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518516, 36518521

Abstract:

A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e. g. , about 1. 2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e. g. , about 1. 2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

US Patent:

6515902, Feb 4, 2003

Filed:

Jun 4, 2001

Appl. No.:

09/873643

Inventors:

Michael A. Van Buskirk - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518518, 36518529, 36518909

Abstract:

A memory device is disclosed having a memory cell in electrical communication with a node, and operative to indicate a binary value associated with data stored in the memory cell during a read operation when a first voltage is applied to the memory cell. The memory device includes a voltage booster connected between the node and a supply voltage which provides a boosted voltage to the node during the read operation, wherein the boosted voltage is greater than the supply voltage. A method is also disclosed for reading data stored in a memory cell, comprising applying a boosted voltage to a node in electrical communication with the memory cell, wherein the boosted voltage is greater that a supply voltage, and sensing a current associated with the memory cell in order to indicate a binary value associated with data stored in the memory cell during a read operation.

US Patent:

6529412, Mar 4, 2003

Filed:

Jan 16, 2002

Appl. No.:

10/050257

Inventors:

Michael A. Van Buskirk - Saratoga CA
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1600

US Classification:

36518521, 36518516

Abstract:

A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line precharge and hold circuit which is operable to apply and maintain a source terminal voltage (e. g. , about 0 volts, ground) to a bit line associated with the source terminal of a cell adjacent to the cell which is sensed during a read operation, wherein the applied source terminal voltage is substantially the same as the bit line virtual ground voltage applied to the source terminal bit line of the selected memory cell to be sensed. The system also includes a drain bit line circuit operable to generate a drain terminal voltage for a drain terminal of a selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a source terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

US Patent:

6541816, Apr 1, 2003

Filed:

Jun 27, 2001

Appl. No.:

09/893026

Inventors:

Mark T. Ramsbey - Sunnyvale CA
Jean Y. Yang - Sunnyvale CA
Hidehiko Shiraiwa - San Jose CA
Michael A. Van Buskirk - Saratoga CA
David M. Rogers - Sunnyvale CA
Ravi S. Sunkavalli - Santa Clara CA
Janet S. Wang - San Francisco CA
Narbeh Derhacobian - Belmont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

International Classification:

H01L 29792

US Classification:

257324

Abstract:

One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.