Michael S Wasserman

US Patent:

6654021, Nov 25, 2003

Filed:

May 18, 2001

Appl. No.:

09/861461

Inventors:

Michael A. Wasserman - Redwood City CA
Michael G. Lavelle - Saratoga CA
David C. Kehlet - Los Altos CA
Nathaniel David Naegle - Pleasanton CA
Steven Te-Chun Yu - Fremont CA
Glenn Gracon - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1318

US Classification:

345535, 345537

Abstract:

A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

US Patent:

6670959, Dec 30, 2003

Filed:

May 18, 2001

Appl. No.:

09/861481

Inventors:

Michael A. Wasserman - Redwood City CA
Michael G. Lavelle - Saratoga CA
David C. Kehlet - Los Altos CA
Glenn Gracon - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1318

US Classification:

345535, 345545

Abstract:

A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.

US Patent:

6784881, Aug 31, 2004

Filed:

Jan 4, 2002

Appl. No.:

10/037410

Inventors:

Michael A. Wasserman - Redwood City CA
Michael G. Lavelle - Saratoga CA
Justin Michael Mahan - Newark CA
David Naegle - Pleasanton CA
Glenn J. Gracon - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G09G 500

US Classification:

345213, 348513

Abstract:

A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.

US Patent:

6819327, Nov 16, 2004

Filed:

May 18, 2001

Appl. No.:

09/861469

Inventors:

Michael A. Wasserman - Redwood City CA
Steven Te-Chun Yu - Fremont CA
Justin M. Mahan - Newark CA
Michael W. Schimpf - Pacific Grove CA
Glenn Gracon - Palo Alto CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G09G 500

US Classification:

345581, 714732, 714 37, 714 45

Abstract:

A signature capture and analysis system suitable for use in a high performance computer graphics system is described. The system employs a distributed network of signature analysis registers (SARs) which may be configured to capture and accumulate information from one or more channels of data over pre-defined periods of time. The SARs may be so distributed to allow for the isolation of faults to a sub-system level. The signature values developed in these SARs are, in some cases pre-seeded, and may include contributions from both data and control signals. Checking of the signature values against known good or expected outcomes is provided for. In some cases the SARs may be implemented as linear hybrid cellular automatons.

US Patent:

6833834, Dec 21, 2004

Filed:

Dec 12, 2001

Appl. No.:

10/021096

Inventors:

Michael A. Wasserman - Redwood City CA
Michael G. Lavelle - Saratoga CA
David C. Kehlet - Los Altos CA
Yan Yan Tang - Mountain View CA
Ewa M. Kubalska - San Jose CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1300

US Classification:

345537, 345545, 345574, 345570

Abstract:

A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

US Patent:

6864900, Mar 8, 2005

Filed:

May 18, 2001

Appl. No.:

09/861467

Inventors:

Michael A. Wasserman - Redwood City CA, US
Michael G. Lavelle - Saratoga CA, US
Elena M. Ing - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G09G005/00
G09G005/36

US Classification:

345672, 345559

Abstract:

A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.

US Patent:

6940514, Sep 6, 2005

Filed:

Apr 26, 2004

Appl. No.:

10/831972

Inventors:

Michael A. Wasserman - Redwood City CA, US
Elena M. Ing - Sunnyvale CA, US
Vannessa M. Nhan - San Jose CA, US
Nandini Ramani - Saratoga CA, US
Charles P. Chang - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06T001/20

US Classification:

345506, 345559

Abstract:

A system and method are disclosed for a rasterization pipeline with a parallel initialization path that may provide an increased rate of triangle processing. The edge walker, span walker, and sample generator modules of a rasterization pipeline may be modified to enable the next primitive in the sequence of primitives to be initialized, while the current primitive is processed. Consequently, these two processes that were done in series may now be done in parallel. Data transmitted between modules may be separated into initialization data (data the module needs to define a primitive) and primitive data (the processed output of each module). The second path is for additional initialization data, which allows each of these modules to receive the initialization data for the next primitive, while processing the primitive data for the current primitive.

US Patent:

6943797, Sep 13, 2005

Filed:

Jun 30, 2003

Appl. No.:

10/611271

Inventors:

Michael A. Wasserman - Redwood City CA, US
Ewa M. Kubalska - San Jose CA, US
Brian D. Emberling - San Mateo CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06T001/20

US Classification:

345506, 345505, 345519, 345418

Abstract:

A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.