Michael E Wiles

US Patent:

40042839, Jan 18, 1977

Filed:

Oct 30, 1974

Appl. No.:

5/519139

Inventors:

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Charles Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

G06F 918

US Classification:

3401725

Abstract:

A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. The digital system uses a multi-level interrupt circuit arrangement including a masked interrupt request input responsive to a multi-plexed interrupt request from peripheral circuits of the system and a non-masked interrupt request input which activates circuitry internal to the microprocessor chip for bypassing program control in initiating an interrupt sequence.

US Patent:

40878554, May 2, 1978

Filed:

Sep 17, 1975

Appl. No.:

5/614109

Inventors:

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Rodney H. Orgill - Norristown PA
Charles I. Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 300
G06F 1300

US Classification:

364200

Abstract:

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

US Patent:

40042812, Jan 18, 1977

Filed:

Oct 30, 1974

Appl. No.:

5/519133

Inventors:

Thomas H. Bennett - Scottsdale AZ
Anthony E. Kouvoussis - Phoenix AZ
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

G06F 900

US Classification:

3401725

Abstract:

A program register is coupled between a data bus N bits wide and an address bus N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. For certain instructions, the address bus is utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter, depending on the type of instruction being executed. The address bus is divided into two sections, each N bits wide, one for transferring higher order address bits and the other for independently transferring lower order address bits.

US Patent:

41457510, Mar 20, 1979

Filed:

Apr 18, 1977

Appl. No.:

5/788184

Inventors:

Earl F. Carlow - Scottsdale AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Charles Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 304
G06F 1300
G11C 900

US Classification:

364900

Abstract:

The peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral system data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.

US Patent:

40695107, Jan 17, 1978

Filed:

May 24, 1976

Appl. No.:

5/689212

Inventors:

Earl F. Carlow - Scottsdale AZ
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

G06F 304
G06F 918

US Classification:

364200

Abstract:

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers. Control circuits include an interrupt/status logic circuit for transmitting control signals to and receiving interrupt signals from a peripheral unit coupled to the interface circuit.

US Patent:

40866270, Apr 25, 1978

Filed:

Sep 17, 1975

Appl. No.:

5/614110

Inventors:

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Edward C. Hepworth - Apache Junction AZ
Wilbur L. Mathys - Norristown PA
William D. Mensch - Norristown PA
Rodney H. Orgill - Norristown PA
Charles I. Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 918

US Classification:

364200

Abstract:

A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.

US Patent:

40165469, Apr 5, 1977

Filed:

Sep 17, 1975

Appl. No.:

5/614033

Inventors:

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Anthony E. Kouvoussis - Phoenix AZ
Rodney H. Orgill - Norristown PA
Charles Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

G06F 920

US Classification:

3401725

Abstract:

A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus.

US Patent:

40030288, Jan 11, 1977

Filed:

Oct 30, 1974

Appl. No.:

5/519137

Inventors:

Thomas H. Bennett - Scottsdale AZ
Earl F. Carlow - Scottsdale AZ
Charles Peddle - Norristown PA
Michael F. Wiles - Phoenix AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

G06F 918
G06F 920

US Classification:

3401725

Abstract:

Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.