Michael Lester Wise

US Patent:

6348395, Feb 19, 2002

Filed:

Jun 7, 2000

Appl. No.:

09/589818

Inventors:

Lawrence A. Clevenger - LaGrangeville NY
Louis L. C. Hsu - Fishkill NY
Jeremy K. Stephens - New Windsor NY
Michael Wise - Lagrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

438424, 438296, 438589, 438634

Abstract:

A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers.

US Patent:

6379222, Apr 30, 2002

Filed:

Jun 14, 1999

Appl. No.:

09/333228

Inventors:

Michael Lester Wise - Poughkeepsie NY
Jeremy Kaspar Stephens - Wappingers Falls NY
Suri G. Hedge - Hollowville NY

Assignee:

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

International Classification:

B24B 100

US Classification:

451 41, 451 7, 451 53, 451285

Abstract:

Areas of different temperatures are provided on a semiconductor wafer to improve uniformity in polishing rates during CMP.

US Patent:

6420216, Jul 16, 2002

Filed:

Mar 14, 2000

Appl. No.:

09/525729

Inventors:

Larry Clevenger - LaGrangeville NY
Louis L. C. Hsu - Fishkill NY
Chandrasekhar Narayan - Hopewell Junction NY
Jeremy K. Stephens - New Windsor NY
Michael Wise - LaGrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corp. - San Jose CA

International Classification:

H01L 2182

US Classification:

438132, 438333

Abstract:

An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride.

US Patent:

6437401, Aug 20, 2002

Filed:

Apr 3, 2001

Appl. No.:

09/824957

Inventors:

Jack A. Mandelman - Stormville NY
Stephan Kudelka - Fishkill NY
Andreas Knorr - Fishkill NY
Stephen Rahn - LaGrangeville NY
Helmut Tews - Poughkeepsie NY
Michael Wise - Lagrangeville NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257330, 257331, 257328

Abstract:

A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

US Patent:

6442637, Aug 27, 2002

Filed:

Aug 12, 1999

Appl. No.:

09/374058

Inventors:

Jeffrey C. Hawkins - Redwood City CA
Peter Skillman - San Carlos CA
Michael Wise - Los Altos Hills CA
John Raff - Menlo Park CA
Daniel Sung-Hwe Kim - Palo Alto CA
Dennis Boyle - Palo Alto CA

Assignee:

Handspring, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

710300, 361686

Abstract:

An expandable mobile computer system is described. The mobile computer system includes a peripheral expansion interface that allows a large number of different sized expansion peripherals to be created and used with the mobile computer system. A pair of rails forms a first opening of the peripheral expansion interface wherein an expansion peripheral device may be inserted. Large expansion peripherals may extend in a first dimension out of that first opening. The rails also form a second opening along a second dimension orthogonal to the first dimension. Large expansion peripherals may also extend outward from the peripheral expansion interface in the second dimension.

US Patent:

D468722, Jan 14, 2003

Filed:

Dec 24, 2001

Appl. No.:

29/152533

Inventors:

Peter Schmidt - Campbell CA
Jeff Jones - Los Altos CA
John Magnasco - San Jose CA
Joseph Myatt - En Cintas CA
Michael Wise - Los Altos CA

Assignee:

Hello Direct, Inc. - San Jose CA

International Classification:

1401

US Classification:

D14205

US Patent:

6596580, Jul 22, 2003

Filed:

Oct 18, 2001

Appl. No.:

09/982574

Inventors:

Jingyu Lian - Walkkill NY
Greg Costrini - Hopewell Junction NY
Laertis Economikos - Wappingers Falls NY
Michael Wise - Lagrangeville NY

Assignee:

Infineon Technologies AG
International Business Machines Corporation - Armonk NY

International Classification:

H01L 218242

US Classification:

438253, 438 3, 438396, 257303, 257306, 257310

Abstract:

The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.

US Patent:

D482359, Nov 18, 2003

Filed:

Oct 6, 2001

Appl. No.:

29/109342

Inventors:

Peter Skillman - San Carlos CA 94070
Jeffrey C. Hawkins - Redwood City CA 94062
Michael Wise - Los Altos Hills CA 94024
John Raff - Menlo Park CA 94025
Daniel Sung-Hwe Kim - Palo Alto CA 94306
Dennis Boyle - Palo Alto CA 94301

International Classification:

1402

US Classification:

D14341